Simulation Results: hmac

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.39 %
  • code
  • 97.14 %
  • assert
  • 96.70 %
  • func
  • 44.34 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.400s 8707.223us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.730s 114.172us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.720s 167.695us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.360s 1471.180us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.090s 217.325us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.300s 45.731us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.720s 167.695us 1 1 100.00
hmac_csr_aliasing 2.090s 217.325us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 18.760s 1614.292us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 16.070s 458.528us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 173.350s 38522.067us 1 1 100.00
hmac_test_sha384_vectors 395.300s 13812.789us 1 1 100.00
hmac_test_sha512_vectors 378.210s 140687.350us 1 1 100.00
hmac_test_hmac256_vectors 6.390s 245.749us 1 1 100.00
hmac_test_hmac384_vectors 6.990s 248.792us 1 1 100.00
hmac_test_hmac512_vectors 7.990s 251.134us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.000s 9397.173us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 166.460s 1553.782us 1 1 100.00
error 1 1 100.00
hmac_error 57.160s 10239.717us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 61.700s 1961.477us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.400s 8707.223us 1 1 100.00
hmac_long_msg 18.760s 1614.292us 1 1 100.00
hmac_back_pressure 16.070s 458.528us 1 1 100.00
hmac_datapath_stress 166.460s 1553.782us 1 1 100.00
hmac_burst_wr 12.000s 9397.173us 1 1 100.00
hmac_stress_all 789.220s 40296.724us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.400s 8707.223us 1 1 100.00
hmac_long_msg 18.760s 1614.292us 1 1 100.00
hmac_back_pressure 16.070s 458.528us 1 1 100.00
hmac_datapath_stress 166.460s 1553.782us 1 1 100.00
hmac_wipe_secret 61.700s 1961.477us 1 1 100.00
hmac_test_sha256_vectors 173.350s 38522.067us 1 1 100.00
hmac_test_sha384_vectors 395.300s 13812.789us 1 1 100.00
hmac_test_sha512_vectors 378.210s 140687.350us 1 1 100.00
hmac_test_hmac256_vectors 6.390s 245.749us 1 1 100.00
hmac_test_hmac384_vectors 6.990s 248.792us 1 1 100.00
hmac_test_hmac512_vectors 7.990s 251.134us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.400s 8707.223us 1 1 100.00
hmac_long_msg 18.760s 1614.292us 1 1 100.00
hmac_back_pressure 16.070s 458.528us 1 1 100.00
hmac_datapath_stress 166.460s 1553.782us 1 1 100.00
hmac_burst_wr 12.000s 9397.173us 1 1 100.00
hmac_error 57.160s 10239.717us 1 1 100.00
hmac_wipe_secret 61.700s 1961.477us 1 1 100.00
hmac_test_sha256_vectors 173.350s 38522.067us 1 1 100.00
hmac_test_sha384_vectors 395.300s 13812.789us 1 1 100.00
hmac_test_sha512_vectors 378.210s 140687.350us 1 1 100.00
hmac_test_hmac256_vectors 6.390s 245.749us 1 1 100.00
hmac_test_hmac384_vectors 6.990s 248.792us 1 1 100.00
hmac_test_hmac512_vectors 7.990s 251.134us 1 1 100.00
hmac_stress_all 789.220s 40296.724us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 789.220s 40296.724us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.550s 21.333us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.780s 16.530us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.260s 174.091us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.260s 174.091us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.730s 114.172us 1 1 100.00
hmac_csr_rw 0.720s 167.695us 1 1 100.00
hmac_csr_aliasing 2.090s 217.325us 1 1 100.00
hmac_same_csr_outstanding 1.030s 23.655us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.730s 114.172us 1 1 100.00
hmac_csr_rw 0.720s 167.695us 1 1 100.00
hmac_csr_aliasing 2.090s 217.325us 1 1 100.00
hmac_same_csr_outstanding 1.030s 23.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.850s 63.684us 1 1 100.00
hmac_tl_intg_err 3.040s 1481.312us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.040s 1481.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.400s 8707.223us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.090s 212.277us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 40.630s 3765.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.840s 30.484us 1 1 100.00