Simulation Results: i2c

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.97 %
  • code
  • 81.54 %
  • assert
  • 96.19 %
  • func
  • 77.17 %
  • line
  • 96.41 %
  • branch
  • 92.33 %
  • cond
  • 84.89 %
  • toggle
  • 89.45 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
92.68%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 12.740s 1156.986us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 20.780s 1066.400us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.640s 28.750us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.680s 134.289us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.420s 364.351us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 0.980s 67.421us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.850s 40.809us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.680s 134.289us 1 1 100.00
i2c_csr_aliasing 0.980s 67.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.650s 62.662us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 103.710s 22287.563us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 284.000s 11992.452us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.590s 17.335us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 92.730s 11175.549us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 33.310s 7453.199us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.830s 691.056us 1 1 100.00
i2c_host_fifo_fmt_empty 2.440s 798.803us 1 1 100.00
i2c_host_fifo_reset_rx 5.160s 169.351us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 56.170s 15061.046us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 12.880s 4027.494us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 2.380s 395.427us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 1.840s 3952.782us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 66.770s 11784.324us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.050s 655.020us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 15.490s 6650.580us 1 1 100.00
i2c_target_intr_smoke 2.450s 11117.245us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.810s 618.757us 1 1 100.00
i2c_target_fifo_reset_tx 1.100s 643.713us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 4.380s 16367.966us 1 1 100.00
i2c_target_stress_rd 15.490s 6650.580us 1 1 100.00
i2c_target_intr_stress_wr 9.770s 14274.070us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.050s 1287.241us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1.220s 157.415us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.810s 14021.630us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.450s 247.168us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.160s 233.784us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.970s 93.630us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 284.000s 11992.452us 1 1 100.00
i2c_host_perf_precise 7.890s 520.942us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 12.880s 4027.494us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.500s 441.143us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.030s 1124.598us 1 1 100.00
i2c_target_nack_acqfull_addr 1.540s 485.176us 1 1 100.00
i2c_target_nack_txstretch 1.060s 648.424us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 5.430s 220.253us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.430s 4904.303us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.630s 27.307us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.630s 20.308us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.510s 149.275us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.510s 149.275us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.640s 28.750us 1 1 100.00
i2c_csr_rw 0.680s 134.289us 1 1 100.00
i2c_csr_aliasing 0.980s 67.421us 1 1 100.00
i2c_same_csr_outstanding 0.710s 24.128us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.640s 28.750us 1 1 100.00
i2c_csr_rw 0.680s 134.289us 1 1 100.00
i2c_csr_aliasing 0.980s 67.421us 1 1 100.00
i2c_same_csr_outstanding 0.710s 24.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.150s 298.164us 1 1 100.00
i2c_sec_cm 0.770s 259.701us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.150s 298.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 23.330s 766.967us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.760s 208.444us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 6.140s 601.961us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 71207168531368924354247947153496164693736633688871458124439809114372758204969 85
UVM_INFO @ 62661695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 16636661100104047080913649174788288548559418285138160144962961357557303901365 107
UVM_INFO @ 22287563005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 107516409165992865523762494211232831782777130480274965632616993805015567427479 104
UVM_INFO @ 766967500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 48021065508767393520892939876360708953217630783774962983833956475700167016428 90
UVM_INFO @ 601960734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 9687722745685452765039290694097008071383239057710314735680721050031860461849 89
UVM_INFO @ 3952782202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 32301233980253602297470070378293048832547786023009484967993022220274560106869 83
UVM_INFO @ 208443636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---