Simulation Results: keymgr

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.52 %
  • code
  • 96.60 %
  • assert
  • 97.49 %
  • func
  • 68.47 %
  • line
  • 98.96 %
  • branch
  • 97.99 %
  • cond
  • 93.00 %
  • toggle
  • 97.72 %
  • FSM
  • 95.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.550s 41.394us 1 1 100.00
random 1 1 100.00
keymgr_random 2.630s 108.257us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.890s 52.235us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.870s 27.531us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 9.040s 261.332us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 6.830s 1513.115us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.650s 214.078us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.870s 27.531us 1 1 100.00
keymgr_csr_aliasing 6.830s 1513.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 3.360s 309.418us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 1.840s 74.219us 1 1 100.00
keymgr_sideload_kmac 3.890s 456.264us 1 1 100.00
keymgr_sideload_aes 1.730s 313.656us 1 1 100.00
keymgr_sideload_otbn 1.980s 357.828us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.260s 1049.531us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.430s 190.747us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.080s 183.176us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.610s 598.458us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.680s 32.135us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 4.920s 1583.933us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 26.970s 3189.533us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.760s 61.678us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.680s 17.808us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.850s 90.781us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.850s 90.781us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.890s 52.235us 1 1 100.00
keymgr_csr_rw 0.870s 27.531us 1 1 100.00
keymgr_csr_aliasing 6.830s 1513.115us 1 1 100.00
keymgr_same_csr_outstanding 1.770s 60.023us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.890s 52.235us 1 1 100.00
keymgr_csr_rw 0.870s 27.531us 1 1 100.00
keymgr_csr_aliasing 6.830s 1513.115us 1 1 100.00
keymgr_same_csr_outstanding 1.770s 60.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
keymgr_tl_intg_err 2.110s 100.269us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 3.850s 711.003us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 3.850s 711.003us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 3.850s 711.003us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 3.850s 711.003us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 7.760s 4925.300us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 2.110s 100.269us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 3.850s 711.003us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 3.360s 309.418us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.630s 108.257us 1 1 100.00
keymgr_csr_rw 0.870s 27.531us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.630s 108.257us 1 1 100.00
keymgr_csr_rw 0.870s 27.531us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.630s 108.257us 1 1 100.00
keymgr_csr_rw 0.870s 27.531us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.430s 190.747us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.680s 32.135us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.680s 32.135us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.630s 108.257us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 12.250s 659.745us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.800s 367.549us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.430s 190.747us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.800s 367.549us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.800s 367.549us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.800s 367.549us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.400s 704.812us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.800s 367.549us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 2.840s 491.828us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 49348016115524939490489910009190962017951068759721154336063100215031628364119 227
UVM_INFO @ 491828042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---