Simulation Results: kmac/unmasked

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.22 %
  • code
  • 88.27 %
  • assert
  • 97.90 %
  • func
  • 90.48 %
  • line
  • 97.14 %
  • branch
  • 94.71 %
  • cond
  • 90.91 %
  • toggle
  • 99.92 %
  • FSM
  • 58.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 27.040s 2014.262us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.890s 82.181us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.870s 65.636us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 6.330s 9701.831us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.480s 414.196us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.360s 53.462us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.870s 65.636us 1 1 100.00
kmac_csr_aliasing 3.480s 414.196us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.650s 43.154us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 0.990s 105.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1724.540s 70848.737us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 222.410s 14926.047us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 30.460s 6895.868us 1 1 100.00
kmac_test_vectors_sha3_256 1078.180s 33466.161us 1 1 100.00
kmac_test_vectors_sha3_384 19.610s 3376.527us 1 1 100.00
kmac_test_vectors_sha3_512 12.450s 2011.022us 1 1 100.00
kmac_test_vectors_shake_128 2052.010s 136764.149us 1 1 100.00
kmac_test_vectors_shake_256 1875.200s 176894.009us 1 1 100.00
kmac_test_vectors_kmac 1.870s 87.252us 1 1 100.00
kmac_test_vectors_kmac_xof 1.950s 105.888us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 72.660s 1585.223us 1 1 100.00
app 1 1 100.00
kmac_app 64.080s 20552.012us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 57.540s 22030.280us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 124.990s 5681.208us 1 1 100.00
error 1 1 100.00
kmac_error 15.330s 298.968us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 3.740s 4235.197us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 1.460s 124.338us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 23.490s 13019.334us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 8.020s 658.448us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 31.930s 11119.374us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.020s 133.755us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 20.530s 13293.816us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.690s 127.254us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.690s 16.929us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.490s 229.624us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.490s 229.624us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.890s 82.181us 1 1 100.00
kmac_csr_rw 0.870s 65.636us 1 1 100.00
kmac_csr_aliasing 3.480s 414.196us 1 1 100.00
kmac_same_csr_outstanding 1.570s 39.055us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.890s 82.181us 1 1 100.00
kmac_csr_rw 0.870s 65.636us 1 1 100.00
kmac_csr_aliasing 3.480s 414.196us 1 1 100.00
kmac_same_csr_outstanding 1.570s 39.055us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.560s 345.899us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.560s 345.899us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.560s 345.899us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.560s 345.899us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 1.910s 151.871us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 24.660s 3825.936us 1 1 100.00
kmac_tl_intg_err 1.890s 404.372us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 1.890s 404.372us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.020s 133.755us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 27.040s 2014.262us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 72.660s 1585.223us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.560s 345.899us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 24.660s 3825.936us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 24.660s 3825.936us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 24.660s 3825.936us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 27.040s 2014.262us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.020s 133.755us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 24.660s 3825.936us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 74.700s 11700.763us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 27.040s 2014.262us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 17.880s 2043.462us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 100366007564881806071498041277680233316595676936981698768459747813226282323534 100
UVM_INFO @ 2043461708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---