Simulation Results: lc_ctrl/volatile_unlock_disabled

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.19 %
  • code
  • 84.08 %
  • assert
  • 94.13 %
  • func
  • 92.35 %
  • line
  • 97.19 %
  • branch
  • 94.00 %
  • cond
  • 79.59 %
  • toggle
  • 87.02 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.240s 39.424us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.910s 37.137us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 55.322us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.350s 358.621us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 35.228us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.860s 29.703us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 55.322us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 35.228us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.150s 543.961us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.520s 1603.035us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.690s 71.339us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.710s 349.142us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.200s 4762.316us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_ctrl_prog_failure 1.710s 349.142us 1 1 100.00
lc_ctrl_errors 9.200s 4762.316us 1 1 100.00
lc_ctrl_security_escalation 5.140s 622.511us 1 1 100.00
lc_ctrl_jtag_state_failure 23.830s 11375.891us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.050s 7937.809us 1 1 100.00
lc_ctrl_jtag_errors 47.420s 2842.685us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.540s 161.536us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.750s 618.479us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.050s 7937.809us 1 1 100.00
lc_ctrl_jtag_errors 47.420s 2842.685us 1 1 100.00
lc_ctrl_jtag_access 2.540s 168.287us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.110s 2709.825us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.410s 117.887us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.870s 384.366us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.530s 933.576us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.990s 2361.659us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.080s 139.565us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.610s 229.605us 1 1 100.00
lc_ctrl_jtag_alert_test 0.780s 21.711us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 11.670s 3100.859us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.830s 25.255us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 50.250s 8494.782us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.960s 20.430us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.230s 423.067us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.230s 423.067us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.910s 37.137us 1 1 100.00
lc_ctrl_csr_rw 0.850s 55.322us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 35.228us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.910s 65.758us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.910s 37.137us 1 1 100.00
lc_ctrl_csr_rw 0.850s 55.322us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 35.228us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.910s 65.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.430s 1222.742us 1 1 100.00
lc_ctrl_tl_intg_err 2.260s 433.081us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.260s 433.081us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.520s 1603.035us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_ctrl_sec_cm 5.430s 1222.742us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_ctrl_sec_cm 5.430s 1222.742us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_ctrl_sec_cm 5.430s 1222.742us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_ctrl_sec_cm 5.430s 1222.742us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_ctrl_sec_cm 5.430s 1222.742us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_ctrl_sec_cm 5.430s 1222.742us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_ctrl_sec_cm 5.430s 1222.742us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.410s 269.536us 1 1 100.00
lc_ctrl_sec_cm 5.430s 1222.742us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.140s 622.511us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.150s 543.961us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.750s 618.479us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.240s 497.287us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.240s 497.287us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.560s 2101.745us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.840s 981.873us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.840s 981.873us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 2.710s 105.949us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 93088420489162122616858258231905230160900081054750321498043454941117208499470 156
UVM_INFO @ 105948680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---