Simulation Results: lc_ctrl/volatile_unlock_enabled

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.41 %
  • code
  • 83.33 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 78.94 %
  • toggle
  • 81.80 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.730s 42.927us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 183.295us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 54.499us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.370s 55.513us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 21.127us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.920s 70.263us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 54.499us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 21.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.560s 284.819us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.770s 975.029us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.790s 41.291us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.730s 76.007us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.290s 3386.404us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_ctrl_prog_failure 1.730s 76.007us 1 1 100.00
lc_ctrl_errors 5.290s 3386.404us 1 1 100.00
lc_ctrl_security_escalation 5.460s 460.448us 1 1 100.00
lc_ctrl_jtag_state_failure 28.970s 2919.132us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.080s 302.030us 1 1 100.00
lc_ctrl_jtag_errors 69.030s 8443.062us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.740s 204.543us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.920s 3130.331us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.080s 302.030us 1 1 100.00
lc_ctrl_jtag_errors 69.030s 8443.062us 1 1 100.00
lc_ctrl_jtag_access 3.440s 173.460us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.250s 11114.322us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.130s 124.805us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.830s 109.972us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.120s 6762.312us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.500s 772.638us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.900s 26.851us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.070s 168.674us 1 1 100.00
lc_ctrl_jtag_alert_test 1.060s 286.774us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.220s 75.786us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.670s 50.954us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 103.320s 5560.417us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.870s 30.751us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.090s 33.984us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.090s 33.984us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 183.295us 1 1 100.00
lc_ctrl_csr_rw 0.850s 54.499us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 21.127us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.910s 51.097us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 183.295us 1 1 100.00
lc_ctrl_csr_rw 0.850s 54.499us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 21.127us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.910s 51.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.080s 121.998us 1 1 100.00
lc_ctrl_tl_intg_err 1.470s 47.079us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.470s 47.079us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.770s 975.029us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_ctrl_sec_cm 5.080s 121.998us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_ctrl_sec_cm 5.080s 121.998us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_ctrl_sec_cm 5.080s 121.998us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_ctrl_sec_cm 5.080s 121.998us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_ctrl_sec_cm 5.080s 121.998us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_ctrl_sec_cm 5.080s 121.998us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_ctrl_sec_cm 5.080s 121.998us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.040s 387.857us 1 1 100.00
lc_ctrl_sec_cm 5.080s 121.998us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.460s 460.448us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.560s 284.819us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.920s 3130.331us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.420s 1269.422us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.420s 1269.422us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.900s 942.691us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.990s 1477.739us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.990s 1477.739us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 32.990s 19487.426us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 26753198800101873488926427950762447938166425538831939052324976103628128583027 14501
UVM_INFO @ 19487426028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---