Simulation Results: otbn

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.40 %
  • code
  • 95.29 %
  • assert
  • 89.59 %
  • func
  • 98.31 %
  • block
  • 99.39 %
  • line
  • 99.54 %
  • branch
  • 92.32 %
  • toggle
  • 91.75 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 49.145us 1 1 100.00
single_binary 1 1 100.00
otbn_single 13.000s 103.022us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 112.686us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 17.161us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 4.000s 55.016us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 115.072us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 951.517us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 17.161us 1 1 100.00
otbn_csr_aliasing 4.000s 115.072us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 52.000s 3105.721us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 23.000s 1669.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 23.000s 77.030us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 43.000s 605.051us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 38.000s 139.480us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 26.000s 245.787us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 14.000s 70.178us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 25.213us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 36.902us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 114.706us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 54.804us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 39.551us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 39.551us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 112.686us 1 1 100.00
otbn_csr_rw 3.000s 17.161us 1 1 100.00
otbn_csr_aliasing 4.000s 115.072us 1 1 100.00
otbn_same_csr_outstanding 3.000s 40.607us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 112.686us 1 1 100.00
otbn_csr_rw 3.000s 17.161us 1 1 100.00
otbn_csr_aliasing 4.000s 115.072us 1 1 100.00
otbn_same_csr_outstanding 3.000s 40.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 34.100us 1 1 100.00
otbn_dmem_err 6.000s 54.503us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 13.000s 844.267us 1 1 100.00
otbn_controller_ispr_rdata_err 6.000s 59.642us 1 1 100.00
otbn_mac_bignum_acc_err 5.000s 38.310us 1 1 100.00
otbn_urnd_err 6.000s 55.413us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 12.305us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 14.125us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 18.400us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
otbn_tl_intg_err 10.000s 125.434us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 35.000s 320.334us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 49.145us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 6.000s 54.503us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 34.100us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 125.434us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 14.000s 70.178us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 34.100us 1 1 100.00
otbn_dmem_err 6.000s 54.503us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 25.213us 1 1 100.00
otbn_illegal_mem_acc 4.000s 12.305us 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 13.000s 103.022us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 34.100us 1 1 100.00
otbn_dmem_err 6.000s 54.503us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 25.213us 1 1 100.00
otbn_illegal_mem_acc 4.000s 12.305us 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 14.000s 70.178us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 34.100us 1 1 100.00
otbn_dmem_err 6.000s 54.503us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 25.213us 1 1 100.00
otbn_illegal_mem_acc 4.000s 12.305us 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 13.000s 103.022us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 32.530us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 54.418us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 19.000s 84.632us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 19.000s 84.632us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 82.575us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 114.160us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 4.000s 19.598us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 4.000s 19.598us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 16.800us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 13.000s 103.022us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 13.000s 103.022us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 13.000s 103.022us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 38.000s 139.480us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 13.000s 103.022us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 13.000s 103.022us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 30.285us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 13.000s 103.022us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 93.000s 1405.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 98.000s 784.592us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 67.860us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 51867841278001052736199133028862665397345376611854943688414775451048032021259 182
UVM_INFO @ 784592025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 38960801770184391267130887179635532479703418717935965975892417155204003623311 118
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 19597508 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 19597508 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 19597508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---