Simulation Results: otp_ctrl

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.67 %
  • code
  • 79.57 %
  • assert
  • 93.99 %
  • func
  • 74.44 %
  • line
  • 88.64 %
  • branch
  • 84.30 %
  • cond
  • 92.46 %
  • toggle
  • 87.13 %
  • FSM
  • 45.31 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.230s 101.192us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.000s 1077.857us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.780s 186.963us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.280s 133.824us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 2.590s 85.213us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.380s 565.053us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.310s 1663.478us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.280s 133.824us 1 1 100.00
otp_ctrl_csr_aliasing 4.380s 565.053us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.070s 39.540us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.070s 115.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 11.280s 323.967us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.280s 137.681us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 12.430s 1238.286us 1 1 100.00
otp_ctrl_check_fail 4.680s 1536.466us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 11.070s 5625.228us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 29.710s 27270.608us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 20.790s 8632.356us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 5.900s 462.970us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 9.590s 983.324us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 4.990s 616.177us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 27.950s 5172.170us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 81.050s 18379.247us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.140s 117.992us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.400s 63.115us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.160s 645.920us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.160s 645.920us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.780s 186.963us 1 1 100.00
otp_ctrl_csr_rw 1.280s 133.824us 1 1 100.00
otp_ctrl_csr_aliasing 4.380s 565.053us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.870s 109.986us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.780s 186.963us 1 1 100.00
otp_ctrl_csr_rw 1.280s 133.824us 1 1 100.00
otp_ctrl_csr_aliasing 4.380s 565.053us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.870s 109.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
otp_ctrl_tl_intg_err 7.860s 2577.628us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.860s 2577.628us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.000s 1077.857us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.000s 1077.857us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
otp_ctrl_macro_errs 4.990s 616.177us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
otp_ctrl_macro_errs 4.990s 616.177us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.570s 150.005us 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.280s 137.681us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 4.680s 1536.466us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 29.710s 27270.608us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 29.710s 27270.608us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 29.710s 27270.608us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 29.710s 27270.608us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 29.710s 27270.608us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.000s 1077.857us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 29.710s 27270.608us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.000s 1077.857us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 154.210s 155428.754us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 11.070s 5625.228us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.000s 1077.857us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.000s 1077.857us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 4.990s 616.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 7.830s 7949.200us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 30.270s 1670.763us 1 1 100.00