Simulation Results: pattgen

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 18.678us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 23.659us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 44.826us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 608.479us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 23.752us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 27.632us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 44.826us 1 1 100.00
pattgen_csr_aliasing 1.000s 23.752us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 3600.000s 0.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 13.000s 9044.717us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 63.984us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 1.000s 116.579us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 28.138us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 33.458us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 58.546us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 58.546us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 23.659us 1 1 100.00
pattgen_csr_rw 1.000s 44.826us 1 1 100.00
pattgen_csr_aliasing 1.000s 23.752us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 37.576us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 23.659us 1 1 100.00
pattgen_csr_rw 1.000s 44.826us 1 1 100.00
pattgen_csr_aliasing 1.000s 23.752us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 37.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 38.247us 1 1 100.00
pattgen_sec_cm 1.000s 40.061us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 38.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 71.000s 16495.310us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 438.098us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
pattgen_perf 12754239286998138422396913670756738308435621122321379959861913282182859067521 None
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 12852974336382297080031847429599760769510262045346311310718154243914052152154 117
UVM_ERROR @ 1775951234 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1775951234 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1776367904 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: 1 test run
pattgen_stress_all 7189008382906950798284641183320757156774698162562625726092400156655368668500 125
------------------------------------
Name Type Size Value
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exp_item pattgen_item - @11322