Simulation Results: pwrmgr

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.00 %
  • code
  • 94.64 %
  • assert
  • 96.34 %
  • func
  • 97.03 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 94.63 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.610s 24.569us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.600s 42.804us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.590s 21.826us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.940s 259.490us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.890s 89.367us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.700s 89.340us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.590s 21.826us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 89.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.880s 199.394us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.880s 199.394us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.630s 55.867us 1 1 100.00
pwrmgr_lowpower_invalid 0.610s 135.762us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.690s 60.782us 1 1 100.00
pwrmgr_reset_invalid 0.670s 148.669us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.690s 60.782us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.680s 140.172us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.940s 258.741us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 2.120s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.280s 896.632us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.560s 39.266us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.480s 151.380us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.480s 151.380us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.600s 42.804us 1 1 100.00
pwrmgr_csr_rw 0.590s 21.826us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 89.367us 1 1 100.00
pwrmgr_same_csr_outstanding 0.740s 43.510us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.600s 42.804us 1 1 100.00
pwrmgr_csr_rw 0.590s 21.826us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 89.367us 1 1 100.00
pwrmgr_same_csr_outstanding 0.740s 43.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.590s 10.756us 0 1 0.00
pwrmgr_sec_cm 0.690s 32.759us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.690s 32.759us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.690s 32.759us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.590s 10.756us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.970s 836.010us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.680s 140.172us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.800s 63.940us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.580s 29.732us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.690s 32.759us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.690s 32.759us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.690s 32.759us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.560s 30.066us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.550s 39.651us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.620s 40.339us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 21.826us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 21.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.670s 104.440us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 5.130s 8702.769us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire 2 test runs
pwrmgr_tl_intg_err 90816166068537942653348275853031256333568588298966536459861933799328160840254 87
UVM_INFO @ 10756051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 8292902981385038738205800030306945010982366575297848936721574195312110464055 90
UVM_INFO @ 32758534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_disable_rom_integrity_check 14134709341070780251036746134489811023214072463113865269911240128546953939246 183
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---