Simulation Results: rom_ctrl/64kb

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.30 %
  • code
  • 94.95 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 96.73 %
  • toggle
  • 100.00 %
  • FSM
  • 80.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.260s 1090.357us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.200s 1346.893us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.010s 1069.018us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.170s 3117.722us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.230s 861.344us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.810s 296.422us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.010s 1069.018us 1 1 100.00
rom_ctrl_csr_aliasing 6.230s 861.344us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.140s 834.090us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.670s 296.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.000s 851.475us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 24.290s 828.510us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 10.990s 6663.396us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.780s 287.389us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.070s 296.671us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.070s 296.671us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.200s 1346.893us 1 1 100.00
rom_ctrl_csr_rw 6.010s 1069.018us 1 1 100.00
rom_ctrl_csr_aliasing 6.230s 861.344us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.050s 9021.165us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.200s 1346.893us 1 1 100.00
rom_ctrl_csr_rw 6.010s 1069.018us 1 1 100.00
rom_ctrl_csr_aliasing 6.230s 861.344us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.050s 9021.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.420s 1088.249us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 412.200s 1219.782us 1 1 100.00
rom_ctrl_tl_intg_err 88.360s 1111.299us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 412.200s 1219.782us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 412.200s 1219.782us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 412.200s 1219.782us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 412.200s 1219.782us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.260s 1090.357us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.260s 1090.357us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.260s 1090.357us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 88.360s 1111.299us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
rom_ctrl_kmac_err_chk 10.990s 6663.396us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.600s 8645.201us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.420s 1088.249us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 412.200s 1219.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 175.410s 3870.574us 1 1 100.00