Simulation Results: rstmgr

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.38 %
  • code
  • 99.27 %
  • assert
  • 97.86 %
  • func
  • 95.02 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.40 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.130s 252.608us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.710s 93.493us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.720s 67.860us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.510s 1020.833us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.080s 103.689us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.860s 126.825us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.720s 67.860us 1 1 100.00
rstmgr_csr_aliasing 1.080s 103.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.710s 155.455us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.380s 270.777us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.950s 173.531us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.000s 906.543us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.000s 906.543us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.000s 906.543us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.000s 906.543us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 6.420s 2170.376us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.680s 71.114us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.600s 259.495us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.600s 259.495us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.710s 93.493us 1 1 100.00
rstmgr_csr_rw 0.720s 67.860us 1 1 100.00
rstmgr_csr_aliasing 1.080s 103.689us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 166.152us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.710s 93.493us 1 1 100.00
rstmgr_csr_rw 0.720s 67.860us 1 1 100.00
rstmgr_csr_aliasing 1.080s 103.689us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 166.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 17.150s 17405.584us 1 1 100.00
rstmgr_tl_intg_err 2.300s 979.380us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 17.150s 17405.584us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 17.150s 17405.584us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.300s 979.380us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.830s 102.152us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.020s 1280.454us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.010s 301.077us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 17.150s 17405.584us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.720s 67.860us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.720s 67.860us 1 1 100.00