Simulation Results: rv_timer

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.17 %
  • code
  • 99.92 %
  • assert
  • 96.82 %
  • func
  • 91.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.560s 131.562us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.550s 44.262us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.540s 17.416us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.250s 99.664us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.660s 415.161us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.600s 21.373us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.540s 17.416us 1 1 100.00
rv_timer_csr_aliasing 0.660s 415.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.370s 13223.752us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.620s 889.571us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.670s 160.413us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.670s 160.413us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.350s 10896.820us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.540s 11.459us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.580s 41.427us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.170s 250.892us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.170s 250.892us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 44.262us 1 1 100.00
rv_timer_csr_rw 0.540s 17.416us 1 1 100.00
rv_timer_csr_aliasing 0.660s 415.161us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 36.128us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 44.262us 1 1 100.00
rv_timer_csr_rw 0.540s 17.416us 1 1 100.00
rv_timer_csr_aliasing 0.660s 415.161us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 36.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.780s 175.887us 1 1 100.00
rv_timer_tl_intg_err 1.090s 669.083us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.090s 669.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.800s 324.578us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.730s 44.902us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 11.480s 2361.591us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 16351465726865815207207697986265572023126968918790577512516289987720730500865 83
UVM_INFO @ 324578216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 100823134734971702371143374494377206874087081987029831667081296415560594907008 80
UVM_INFO @ 13223751689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 87413633828416720409299339533774600141977795111637352309740179417212856951631 80
UVM_INFO @ 44901662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---