Simulation Results: spi_device/2p

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.20 %
  • code
  • 92.90 %
  • assert
  • 94.49 %
  • func
  • 56.20 %
  • line
  • 98.66 %
  • branch
  • 97.94 %
  • cond
  • 95.38 %
  • toggle
  • 87.39 %
  • FSM
  • 85.11 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 8.140s 3555.451us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.060s 40.403us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.030s 291.606us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 21.260s 524.969us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.970s 270.412us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.360s 93.208us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.030s 291.606us 1 1 100.00
spi_device_csr_aliasing 4.970s 270.412us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.620s 39.565us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.270s 49.397us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.730s 18.497us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.840s 14.745us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.670s 24.350us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.670s 38.451us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.670s 38.451us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.090s 919.732us 1 1 100.00
spi_device_tpm_sts_read 0.810s 169.212us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 10.580s 9190.843us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.910s 76.987us 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.620s 277.281us 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.620s 277.281us 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.620s 58.936us 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.620s 58.936us 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.620s 58.936us 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.620s 58.936us 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.620s 58.936us 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 9.200s 3633.096us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 2.540s 137.322us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 2.540s 137.322us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 2.540s 137.322us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 23.030s 4410.885us 1 1 100.00
spi_device_read_buffer_direct 2.330s 250.843us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 2.540s 137.322us 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 43.960s 5148.089us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.530s 475.725us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.530s 475.725us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 8.140s 3555.451us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 13.270s 1876.912us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 12.550s 3403.549us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.640s 19.450us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.680s 13.365us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.570s 66.619us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.570s 66.619us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.060s 40.403us 1 1 100.00
spi_device_csr_rw 1.030s 291.606us 1 1 100.00
spi_device_csr_aliasing 4.970s 270.412us 1 1 100.00
spi_device_same_csr_outstanding 2.120s 425.199us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.060s 40.403us 1 1 100.00
spi_device_csr_rw 1.030s 291.606us 1 1 100.00
spi_device_csr_aliasing 4.970s 270.412us 1 1 100.00
spi_device_same_csr_outstanding 2.120s 425.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.950s 497.964us 1 1 100.00
spi_device_tl_intg_err 9.500s 1509.281us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.500s 1509.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 59.960s 15669.174us 1 1 100.00