Simulation Results: sram_ctrl/ret

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.13 %
  • code
  • 82.49 %
  • assert
  • 96.29 %
  • func
  • 94.60 %
  • block
  • 92.64 %
  • line
  • 93.69 %
  • branch
  • 87.32 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 108.953us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 15.390us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.484us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 118.725us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.939us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 94.467us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 13.484us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.939us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 590.223us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 603.623us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 1718.881us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 115.000s 2568.662us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 600.419us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 4.000s 388.161us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 1247.778us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 788.393us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 217.551us 1 1 100.00
sram_ctrl_partial_access_b2b 130.000s 10326.076us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 158.994us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 36.704us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 146.501us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 80.370us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 75.456us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 30.000s 5856.362us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 35.435us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 149.141us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 149.141us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.390us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.484us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.939us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 60.342us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.390us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.484us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.939us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 60.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 813.782us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 750.608us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 203.635us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 750.608us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 203.635us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 80.370us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 80.370us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.484us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 788.393us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 788.393us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 788.393us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 1247.778us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 55.063us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 813.782us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 313.702us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 108.953us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 108.953us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 788.393us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 750.608us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 1247.778us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 750.608us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 750.608us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 108.953us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 750.608us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 44.000s 2518.195us 1 1 100.00