Simulation Results: sysrst_ctrl

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.03 %
  • code
  • 92.91 %
  • assert
  • 94.35 %
  • func
  • 64.83 %
  • line
  • 97.51 %
  • branch
  • 97.40 %
  • cond
  • 95.76 %
  • toggle
  • 99.54 %
  • FSM
  • 74.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.450s 2133.288us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.000s 2463.179us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.500s 2228.624us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.040s 2534.642us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.430s 4041.761us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.000s 2194.211us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 33.180s 75860.514us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.350s 2193.255us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.350s 2091.436us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.000s 2194.211us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.350s 2193.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 173.020s 100538.067us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 126.580s 93992.004us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.480s 3465.777us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.340s 4513.896us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.540s 2511.137us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.290s 2133.351us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.360s 2771.124us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.820s 2628.427us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.990s 10609.211us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 64.190s 39093.395us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 9.430s 9589.759us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.510s 2035.580us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.160s 2075.391us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.590s 2098.863us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.590s 2098.863us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.430s 4041.761us 1 1 100.00
sysrst_ctrl_csr_rw 1.000s 2194.211us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.350s 2193.255us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.450s 10672.887us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.430s 4041.761us 1 1 100.00
sysrst_ctrl_csr_rw 1.000s 2194.211us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.350s 2193.255us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.450s 10672.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 34.360s 22080.132us 1 1 100.00
sysrst_ctrl_tl_intg_err 17.000s 43149.872us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 17.000s 43149.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.000s 12031.557us 1 1 100.00