Simulation Results: uart

 
12/05/2026 15:30:21 DVSim: v1.34.0 sha: d723749 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.82 %
  • code
  • 96.80 %
  • assert
  • 97.12 %
  • func
  • 54.55 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.02 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.500s 493.789us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.590s 16.772us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 15.170us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.180s 135.467us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.720s 50.199us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.860s 30.686us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 15.170us 1 1 100.00
uart_csr_aliasing 0.720s 50.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 9.000s 37979.431us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.500s 493.789us 1 1 100.00
uart_tx_rx 9.000s 37979.431us 1 1 100.00
parity_error 2 2 100.00
uart_intr 11.860s 8281.090us 1 1 100.00
uart_rx_parity_err 26.820s 69667.149us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 9.000s 37979.431us 1 1 100.00
uart_intr 11.860s 8281.090us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 19.990s 61748.477us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 14.790s 36075.093us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 8.930s 8786.089us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 11.860s 8281.090us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 11.860s 8281.090us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 11.860s 8281.090us 1 1 100.00
perf 1 1 100.00
uart_perf 433.440s 27667.833us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.100s 2144.242us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.100s 2144.242us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.210s 1809.389us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.850s 2574.335us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 0.990s 582.001us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.310s 1697.989us 1 1 100.00
long_b2b_transfer 0 1 0.00
uart_long_xfer_wo_dly 162.370s 114553.191us 0 1 0.00
stress_all 1 1 100.00
uart_stress_all 386.750s 463708.183us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.540s 68.791us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 11.821us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.480s 98.418us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.480s 98.418us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.590s 16.772us 1 1 100.00
uart_csr_rw 0.590s 15.170us 1 1 100.00
uart_csr_aliasing 0.720s 50.199us 1 1 100.00
uart_same_csr_outstanding 0.710s 119.179us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.590s 16.772us 1 1 100.00
uart_csr_rw 0.590s 15.170us 1 1 100.00
uart_csr_aliasing 0.720s 50.199us 1 1 100.00
uart_same_csr_outstanding 0.710s 119.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.780s 267.153us 1 1 100.00
uart_tl_intg_err 1.050s 98.907us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.050s 98.907us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 33.280s 3241.751us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 70208453730540189713622581530863795932822212420432654887676534759448352412978 80
UVM_ERROR @ 1780089187 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1780719187 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1781329187 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1781939187 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_long_xfer_wo_dly 47183672645605690289579410832029178161083204868524277341002347043796415082947 85
UVM_ERROR @ 96712930858 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 96815578738 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 98256296146 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_INFO @ 102293387266 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 7/7