Simulation Results

Simulation Results: adc_ctrl

13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
65.32 %

code
91.78 %

assert
91.09 %

func
13.09 %

line
98.16 %

branch
96.47 %

cond
86.35 %

toggle
99.53 %

FSM
78.38 %

Validation stages

V1		100.00%
V2		52.63%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	3.810s	5817.264us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	3.040s	1155.668us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	1.180s	495.736us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	16.870s	26920.905us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	3.330s	1139.462us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.160s	939.351us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	1.180s	495.736us	1	1	100.00
	adc_ctrl_csr_aliasing	3.330s	1139.462us	1	1	100.00

10/19 passed

52.63 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	1.290s	343.072us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	1.150s	493.121us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	0.940s	424.982us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	0.790s	477.593us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	1.010s	451.665us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	1.050s	390.888us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	0.780s	453.963us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	1.270s	405.434us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	5.200s	5457.719us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	3.520s	29975.720us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	105.030s	121191.418us	1	1	100.00
stress_all				0	1	0.00
	adc_ctrl_stress_all	1.450s	947.593us	0	1	0.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	1.000s	416.707us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	1.120s	334.042us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	2.390s	899.010us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	2.390s	899.010us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	3.040s	1155.668us	1	1	100.00
	adc_ctrl_csr_rw	1.180s	495.736us	1	1	100.00
	adc_ctrl_csr_aliasing	3.330s	1139.462us	1	1	100.00
	adc_ctrl_same_csr_outstanding	2.500s	2285.200us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	3.040s	1155.668us	1	1	100.00
	adc_ctrl_csr_rw	1.180s	495.736us	1	1	100.00
	adc_ctrl_csr_aliasing	3.330s	1139.462us	1	1	100.00
	adc_ctrl_same_csr_outstanding	2.500s	2285.200us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	7.340s	3918.699us	1	1	100.00
	adc_ctrl_tl_intg_err	4.460s	4564.743us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	4.460s	4564.743us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	adc_ctrl_stress_all_with_rand_reset	4.820s	5327.568us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				9 test runs
	adc_ctrl_filters_polled	35138079632309936454885718784918357998418520804931555367965072287332092687795	388	UVM_INFO @ 343071723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	104372964175778461878080108612967822080757114851092024512300130940453126704148	388	UVM_INFO @ 493121483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	84856656092743674287116210873811185155892692356512462469445106774915171483424	388	UVM_INFO @ 424981730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	68104065814405139820586493198502547104425166978541743923903506450761508762475	388	UVM_INFO @ 477592515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	53140490826890020550635278436192769617049525512798250667786635720092828165878	388	UVM_INFO @ 451665450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	7074520189181608462248247705527336783104506768632387210839399846055749117020	388	UVM_INFO @ 390887872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	43408821415235557196467482319855202459965697563751623969105713180989376440953	388	UVM_INFO @ 405433660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	85078248034398354946390024170835397468385164055977673969421892305870554041939	388	UVM_INFO @ 453962679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	110424730189409566675098239670706042427546745270739125896912231666778813621095	389	UVM_INFO @ 947593353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---