Simulation Results: alert_handler

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.13 %
  • code
  • 91.55 %
  • assert
  • 98.23 %
  • func
  • 77.60 %
  • line
  • 99.77 %
  • branch
  • 98.42 %
  • cond
  • 91.54 %
  • toggle
  • 85.74 %
  • FSM
  • 82.26 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 2.250s 55.522us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.420s 227.609us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.260s 93.626us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 227.020s 23760.794us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 142.160s 41550.096us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.500s 118.019us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.260s 93.626us 1 1 100.00
alert_handler_csr_aliasing 142.160s 41550.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 75.250s 3252.037us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 8.580s 117.457us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 686.930s 23476.317us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 20.460s 439.675us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 2.250s 55.522us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 13.740s 246.651us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 13.500s 319.117us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 53.930s 2217.487us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 655.430s 12616.659us 1 1 100.00
alert_handler_lpg_stub_clk 1003.980s 114083.860us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 644.660s 15886.197us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 3.240s 868.808us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.630s 38.503us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.090s 14.050us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 3.860s 68.236us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 3.860s 68.236us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.420s 227.609us 1 1 100.00
alert_handler_csr_rw 5.260s 93.626us 1 1 100.00
alert_handler_csr_aliasing 142.160s 41550.096us 1 1 100.00
alert_handler_same_csr_outstanding 16.520s 674.645us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.420s 227.609us 1 1 100.00
alert_handler_csr_rw 5.260s 93.626us 1 1 100.00
alert_handler_csr_aliasing 142.160s 41550.096us 1 1 100.00
alert_handler_same_csr_outstanding 16.520s 674.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 168.960s 5866.478us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 168.960s 5866.478us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 168.960s 5866.478us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 168.960s 5866.478us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 206.150s 10036.939us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
alert_handler_tl_intg_err 44.060s 3714.152us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 44.060s 3714.152us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 168.960s 5866.478us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 2.250s 55.522us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 2.250s 55.522us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 2.250s 55.522us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 2.250s 55.522us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.460s 439.675us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 655.430s 12616.659us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.460s 439.675us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 686.930s 23476.317us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 686.930s 23476.317us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 35.030s 1353.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 108.240s 5754.640us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 72318544903734473966738838237643914193003302936979019353162791255981421400455 93
UVM_INFO @ 2217487207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 60028683321010597681354811233213175055252149951190374329738002130892090181194 182
UVM_INFO @ 868807745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 10123101945366804125345373124421267260908056841966715159208729719561162638353 145
UVM_INFO @ 5754639989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---