Simulation Results: chip

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.12 %
  • code
  • 84.37 %
  • assert
  • 97.37 %
  • func
  • 28.61 %
  • line
  • 93.87 %
  • branch
  • 92.28 %
  • cond
  • 87.24 %
  • toggle
  • 91.32 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.34%
V2S
100.00%
V3
65.38%
unmapped
72.73%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 111.510s 2893.379us 1 1 100.00
chip_sw_example_rom 88.030s 2540.319us 1 1 100.00
chip_sw_example_manufacturer 118.790s 3065.907us 1 1 100.00
chip_sw_example_concurrency 134.570s 2739.304us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 292.360s 6381.543us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 252.200s 4323.311us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 391.990s 5690.714us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3366.250s 29615.072us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 72.970s 2380.095us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3366.250s 29615.072us 1 1 100.00
chip_csr_rw 252.200s 4323.311us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.560s 54.045us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 292.020s 4888.404us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 292.020s 4888.404us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 292.020s 4888.404us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 386.580s 4486.877us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 386.580s 4486.877us 1 1 100.00
chip_sw_uart_tx_rx_idx1 310.830s 4662.591us 1 1 100.00
chip_sw_uart_tx_rx_idx2 318.600s 4489.644us 1 1 100.00
chip_sw_uart_tx_rx_idx3 307.630s 4772.338us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 421.450s 4470.096us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 985.590s 8440.451us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 207.970s 4147.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 172.470s 4994.084us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 172.470s 4994.084us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 186.080s 3197.577us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 234.060s 6300.341us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 166.930s 3638.886us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 1081.670s 16896.785us 1 1 100.00
chip_tap_straps_testunlock0 263.430s 6254.343us 1 1 100.00
chip_tap_straps_rma 432.270s 7302.962us 1 1 100.00
chip_tap_straps_prod 93.990s 2721.810us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 134.270s 3274.633us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 717.160s 9469.781us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 374.890s 5122.902us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 374.890s 5122.902us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 575.500s 8349.118us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1075.410s 12471.010us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 360.670s 4405.729us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 601.560s 5714.119us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3636.970s 18454.137us 1 1 100.00
chip_sw_aes_enc_jitter_en 193.640s 3231.057us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 672.820s 6758.785us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.900s 3085.380us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1544.610s 11857.480us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 157.160s 3296.024us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 320.670s 5904.271us 1 1 100.00
chip_sw_clkmgr_jitter 111.050s 3191.024us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 160.910s 2857.229us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 1 2 50.00
chip_sw_sensor_ctrl_alert 161.520s 2824.311us 0 1 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 208.400s 5109.332us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 132.250s 2730.844us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 208.400s 5109.332us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 156.290s 3258.783us 1 1 100.00
chip_sw_aes_smoketest 179.740s 3400.038us 1 1 100.00
chip_sw_aon_timer_smoketest 190.720s 3494.926us 1 1 100.00
chip_sw_clkmgr_smoketest 132.080s 3011.925us 1 1 100.00
chip_sw_csrng_smoketest 157.770s 3130.190us 1 1 100.00
chip_sw_entropy_src_smoketest 590.850s 6032.611us 1 1 100.00
chip_sw_gpio_smoketest 165.800s 2717.339us 1 1 100.00
chip_sw_hmac_smoketest 163.200s 3014.960us 1 1 100.00
chip_sw_kmac_smoketest 170.970s 3665.473us 1 1 100.00
chip_sw_otbn_smoketest 664.970s 6179.781us 1 1 100.00
chip_sw_pwrmgr_smoketest 225.310s 5834.912us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 241.900s 6268.860us 1 1 100.00
chip_sw_rv_plic_smoketest 141.740s 2669.710us 1 1 100.00
chip_sw_rv_timer_smoketest 164.880s 2625.859us 1 1 100.00
chip_sw_rstmgr_smoketest 122.860s 3263.501us 1 1 100.00
chip_sw_sram_ctrl_smoketest 160.570s 3189.758us 1 1 100.00
chip_sw_uart_smoketest 118.260s 3071.594us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 133.390s 2956.043us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 368.200s 5156.771us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7485.760s 62830.665us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2993.470s 15246.689us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 165.586s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 169.720s 3326.767us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 130.400s 3575.332us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6974.350s 54968.191us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7717.930s 59479.370us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 62.600s 2365.046us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 62.600s 2365.046us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3366.250s 29615.072us 1 1 100.00
chip_same_csr_outstanding 1505.310s 16580.044us 1 1 100.00
chip_csr_hw_reset 292.360s 6381.543us 1 1 100.00
chip_csr_rw 252.200s 4323.311us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3366.250s 29615.072us 1 1 100.00
chip_same_csr_outstanding 1505.310s 16580.044us 1 1 100.00
chip_csr_hw_reset 292.360s 6381.543us 1 1 100.00
chip_csr_rw 252.200s 4323.311us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 10.730s 355.572us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.800s 56.462us 1 1 100.00
xbar_smoke_large_delays 45.270s 7718.602us 1 1 100.00
xbar_smoke_slow_rsp 44.330s 5165.729us 1 1 100.00
xbar_random_zero_delays 12.910s 163.876us 1 1 100.00
xbar_random_large_delays 152.060s 28266.045us 1 1 100.00
xbar_random_slow_rsp 104.740s 13304.490us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 8.690s 89.489us 1 1 100.00
xbar_error_and_unmapped_addr 18.210s 575.495us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 10.410s 378.947us 1 1 100.00
xbar_error_and_unmapped_addr 18.210s 575.495us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 12.760s 266.117us 1 1 100.00
xbar_access_same_device_slow_rsp 323.340s 39843.660us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 12.710s 211.905us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 48.070s 721.888us 1 1 100.00
xbar_stress_all_with_error 83.360s 3422.694us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 119.020s 530.110us 1 1 100.00
xbar_stress_all_with_reset_error 88.620s 550.642us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2993.470s 15246.689us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2663.500s 31602.574us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2949.100s 15104.855us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 170.841s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 105.785s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 15.152s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 99.159s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 202.671s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 169.554s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 152.737s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 146.250s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 28.318s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 33.252s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 171.412s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 182.222s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 90.351s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 152.290s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 153.995s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 19.520s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 18.610s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 18.560s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 18.360s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 18.490s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.910s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 18.040s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.910s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.710s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.850s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 17.720s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 19.380s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17.230s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 18.820s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.780s 10.400us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 170.387s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 130.243s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 130.247s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 117.313s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 196.806s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 5470.030s 29975.364us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5522.300s 29900.694us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3046.970s 17187.835us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3328.630s 16328.037us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2677.590s 34166.302us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2677.590s 34166.302us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 238.990s 3094.207us 1 1 100.00
chip_sw_aes_enc_jitter_en 193.640s 3231.057us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 144.200s 2925.010us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 177.920s 3071.539us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1267.950s 10669.619us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 151.840s 3166.258us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 360.360s 4529.678us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 440.040s 5714.332us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 550.500s 5185.290us 1 1 100.00
chip_plic_all_irqs_10 287.940s 3878.944us 1 1 100.00
chip_plic_all_irqs_20 315.560s 4258.925us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 168.510s 2987.331us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 992.080s 11335.953us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 222.340s 4049.024us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 168.890s 2562.433us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.154s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1044.980s 8151.257us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 869.160s 7022.029us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 785.670s 8047.178us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8743.920s 255608.134us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 211.670s 4243.412us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 225.310s 5834.912us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 211.670s 4243.412us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 477.450s 7630.636us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 477.450s 7630.636us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 242.220s 7313.364us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 381.450s 4635.125us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 531.450s 6367.372us 1 1 100.00
chip_sw_aes_idle 177.920s 3071.539us 1 1 100.00
chip_sw_hmac_enc_idle 222.760s 3577.825us 1 1 100.00
chip_sw_kmac_idle 106.960s 2945.383us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 364.710s 3887.226us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 390.230s 4289.540us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 306.080s 4914.996us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 289.450s 4408.731us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 652.310s 8767.140us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 384.670s 4099.480us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 380.910s 5336.173us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 434.650s 4569.163us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 356.350s 4094.350us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 413.250s 4571.893us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 344.830s 4759.807us 1 1 100.00
chip_sw_ast_clk_outputs 575.500s 8349.118us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 329.490s 5872.498us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 434.650s 4569.163us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 356.350s 4094.350us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 360.670s 4405.729us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 601.560s 5714.119us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3636.970s 18454.137us 1 1 100.00
chip_sw_aes_enc_jitter_en 193.640s 3231.057us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 672.820s 6758.785us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.900s 3085.380us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1544.610s 11857.480us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 157.160s 3296.024us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 320.670s 5904.271us 1 1 100.00
chip_sw_clkmgr_jitter 111.050s 3191.024us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 164.190s 3369.292us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 387.190s 4233.512us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 602.360s 7274.041us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3819.730s 25026.112us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 159.970s 2639.939us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 151.340s 2600.420us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1008.900s 11759.608us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 150.000s 3453.034us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 368.450s 6200.698us 1 1 100.00
chip_sw_flash_init_reduced_freq 1000.300s 22545.584us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 18916.470s 228847.125us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 575.500s 8349.118us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 373.320s 5009.033us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 257.340s 3309.647us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 440.040s 5714.332us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1044.980s 8151.257us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2198.990s 24024.142us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 170.230s 3487.663us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 456.070s 6926.935us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 153.410s 3110.703us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3724.640s 21575.939us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 110.140s 2516.147us 1 1 100.00
chip_sw_edn_entropy_reqs 638.870s 6879.861us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 110.140s 2516.147us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2198.990s 24024.142us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 192.020s 3554.464us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1123.970s 18588.388us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 568.930s 5466.475us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 601.560s 5714.119us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 333.290s 3521.551us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 360.670s 4405.729us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3260.560s 44175.698us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1123.970s 18588.388us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 184.510s 3026.915us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 655.190s 7886.799us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.850s 2963.252us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3260.560s 44175.698us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.850s 2963.252us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.850s 2963.252us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.850s 2963.252us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.850s 2963.252us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 440.040s 5714.332us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 68.680s 3103.667us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 516.960s 5001.897us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 378.060s 4980.435us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 378.060s 4980.435us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 189.110s 3427.764us 1 1 100.00
chip_sw_hmac_enc_jitter_en 170.900s 3085.380us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 222.760s 3577.825us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1118.250s 8456.025us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 681.640s 5843.966us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 385.300s 5558.440us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 365.270s 4878.145us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 381.450s 5853.108us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 246.370s 4411.609us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 655.190s 7886.799us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1544.610s 11857.480us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1304.380s 11867.253us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1267.950s 10669.619us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2092.370s 10066.574us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 128.550s 2928.929us 1 1 100.00
chip_sw_kmac_mode_kmac 167.020s 2698.162us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 157.160s 3296.024us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 655.190s 7886.799us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 302.070s 5379.606us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 129.040s 3144.417us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 878.860s 8212.696us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 106.960s 2945.383us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 360.360s 4529.678us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 1081.670s 16896.785us 1 1 100.00
chip_tap_straps_rma 432.270s 7302.962us 1 1 100.00
chip_tap_straps_prod 93.990s 2721.810us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 145.670s 3230.828us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 302.070s 5379.606us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 302.070s 5379.606us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 302.070s 5379.606us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 737.570s 8063.076us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 197.850s 2963.252us 0 1 0.00
chip_sw_flash_rma_unlocked 3260.560s 44175.698us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 165.990s 3117.269us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 504.120s 7890.637us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 476.560s 7792.756us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 414.290s 6712.781us 0 1 0.00
chip_sw_lc_ctrl_transition 302.070s 5379.606us 1 1 100.00
chip_sw_keymgr_key_derivation 655.190s 7886.799us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 337.230s 10072.650us 1 1 100.00
chip_sw_sram_ctrl_execution_main 436.580s 7290.873us 1 1 100.00
chip_prim_tl_access 68.680s 3103.667us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 329.490s 5872.498us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 384.670s 4099.480us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 380.910s 5336.173us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 434.650s 4569.163us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 356.350s 4094.350us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 413.250s 4571.893us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 344.830s 4759.807us 1 1 100.00
chip_tap_straps_dev 1081.670s 16896.785us 1 1 100.00
chip_tap_straps_rma 432.270s 7302.962us 1 1 100.00
chip_tap_straps_prod 93.990s 2721.810us 1 1 100.00
chip_rv_dm_lc_disabled 171.730s 5747.213us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 137.520s 3114.058us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 90.690s 3467.694us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 65.190s 2468.037us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 173.070s 3194.281us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1338.830s 33004.219us 1 1 100.00
chip_rv_dm_lc_disabled 171.730s 5747.213us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 768.460s 26318.813us 0 1 0.00
chip_sw_lc_walkthrough_prod 706.030s 9243.937us 0 1 0.00
chip_sw_lc_walkthrough_prodend 575.140s 10390.042us 1 1 100.00
chip_sw_lc_walkthrough_rma 341.280s 6379.862us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1338.830s 33004.219us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 59.740s 2121.986us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 67.270s 2851.388us 1 1 100.00
rom_volatile_raw_unlock 148.155s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3721.840s 17315.846us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3636.970s 18454.137us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 531.450s 6367.372us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 531.450s 6367.372us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 531.450s 6367.372us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 248.450s 3367.725us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 302.070s 5379.606us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1123.970s 18588.388us 1 1 100.00
chip_sw_otbn_mem_scramble 248.450s 3367.725us 1 1 100.00
chip_sw_keymgr_key_derivation 655.190s 7886.799us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 374.550s 5480.297us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 144.750s 2824.592us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1123.970s 18588.388us 1 1 100.00
chip_sw_otbn_mem_scramble 248.450s 3367.725us 1 1 100.00
chip_sw_keymgr_key_derivation 655.190s 7886.799us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 374.550s 5480.297us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 144.750s 2824.592us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 302.070s 5379.606us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 246.920s 4263.913us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 145.670s 3230.828us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 165.990s 3117.269us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 504.120s 7890.637us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 476.560s 7792.756us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 414.290s 6712.781us 0 1 0.00
chip_sw_lc_ctrl_transition 302.070s 5379.606us 1 1 100.00
chip_prim_tl_access 68.680s 3103.667us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 68.680s 3103.667us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 913.410s 8370.818us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 71.230s 3218.867us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1094.850s 25550.656us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 213.800s 7108.734us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 359.140s 8635.300us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 393.270s 7007.537us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 981.750s 24286.482us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 783.110s 13071.210us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 477.450s 7630.636us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 925.990s 12196.004us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 282.340s 5713.436us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 71.230s 3218.867us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 240.640s 4224.244us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 196.400s 4043.548us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 229.840s 5468.919us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 139.800s 2877.628us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 613.460s 13231.413us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 639.680s 8716.625us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 978.380s 11570.640us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1767.510s 27278.970us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 148.980s 3421.357us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 440.040s 5714.332us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 337.230s 10072.650us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 337.230s 10072.650us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 978.380s 11570.640us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 613.460s 13231.413us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 282.340s 5713.436us 1 1 100.00
chip_sw_pwrmgr_smoketest 225.310s 5834.912us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 258.110s 5201.849us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 408.200s 6321.972us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 242.660s 3776.788us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 992.080s 11335.953us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 118.920s 2723.961us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 440.040s 5714.332us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 869.160s 7022.029us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 423.860s 4547.325us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 438.630s 4481.016us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 155.300s 3011.524us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 144.750s 2824.592us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 408.200s 6321.972us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 408.200s 6321.972us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 626.390s 9623.579us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 973.440s 13499.640us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 258.110s 5201.849us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 164.480s 3183.905us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 302.680s 6247.280us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 432.270s 7302.962us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 171.730s 5747.213us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 550.500s 5185.290us 1 1 100.00
chip_plic_all_irqs_10 287.940s 3878.944us 1 1 100.00
chip_plic_all_irqs_20 315.560s 4258.925us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 183.770s 3365.761us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 126.230s 2578.722us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2993.470s 15246.689us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 319.850s 5808.215us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 162.660s 3408.464us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 171.710s 2999.522us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 195.270s 3319.030us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 374.550s 5480.297us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 320.670s 5904.271us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 377.370s 8143.886us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 311.860s 7366.755us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 436.580s 7290.873us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 440.040s 5714.332us 1 1 100.00
chip_sw_data_integrity_escalation 374.890s 5122.902us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 639.680s 8716.625us 1 1 100.00
chip_sw_sysrst_ctrl_reset 856.600s 22374.470us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 140.560s 2285.299us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 227.070s 4037.993us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 302.360s 4869.208us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 856.600s 22374.470us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 856.600s 22374.470us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2349.320s 20837.961us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2349.320s 20837.961us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 310.410s 6108.529us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2677.590s 34166.302us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 117.880s 2117.420us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 101.810s 2535.430us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 254.850s 3951.912us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 238.790s 3565.515us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 798.110s 8078.455us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5265.560s 31916.197us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1753.420s 12391.003us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 165.820s 3121.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 159.220s 2932.934us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 95.630s 2507.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9464.290s 71477.220us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1100.210s 6377.500us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 470.890s 14807.585us 0 1 0.00
rom_e2e_jtag_debug_dev 188.630s 4107.182us 0 1 0.00
rom_e2e_jtag_debug_rma 179.220s 4591.510us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 81.590s 3012.961us 0 1 0.00
rom_e2e_jtag_inject_dev 54.250s 2007.507us 0 1 0.00
rom_e2e_jtag_inject_rma 84.320s 2922.344us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 237.964s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 257.830s 3344.588us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 314.120s 2924.791us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 744.440s 5369.239us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1224.550s 9395.198us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 229.990s 2526.261us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 600.090s 5592.276us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 62.700s 2083.241us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 142.080s 3384.494us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 276.780s 6744.137us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 293.620s 5632.178us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 978.380s 11570.640us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 470.890s 14807.585us 0 1 0.00
rom_e2e_jtag_debug_dev 188.630s 4107.182us 0 1 0.00
rom_e2e_jtag_debug_rma 179.220s 4591.510us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 310.780s 5339.723us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 440.040s 5714.332us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5643.740s 38300.824us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5643.740s 38300.824us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 147.600s 3478.785us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 386.580s 4486.877us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2883.450s 18497.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 11 72.73
chip_sival_flash_info_access 192.360s 2778.207us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 295.310s 4603.982us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.730s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 135.960s 2539.809us 1 1 100.00
chip_sw_otp_ctrl_descrambling 139.830s 3396.330us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 243.330s 3929.940us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.109s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 164.090s 3403.275us 1 1 100.00
ate_bootstrap_flash_erase 546.630s 10010.200us 0 1 0.00
ate_bootstrap_one_frame 6049.620s 45348.987us 1 1 100.00
ate_bootstrap_disjoint 9708.640s 84614.406us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 110498448021446826736761293277457456975536015478404159986617783711927336609906 None
---- STDERR ----
Another command (pid=2084440) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 75081267903939193097291495346988400210301728908763157615534296133409368798061 None
Another command (pid=419597) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=409828) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=579256) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 3395495989492772982670422089700012188385838230453079315932929153039854586106 None
Another command (pid=693598) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=585221) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=582001) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 43295510940364467462280677135749385710165172056361547089679777735435053507707 None
---- STDERR ----
Another command (pid=444480) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 65892083763082266962350207896617087424576496092596515941316521107233206682501 None
Another command (pid=689272) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=600643) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=716357) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 114996886974038307005100932364171211651334570696167678263878863882815357306262 None
Another command (pid=1001024) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=987579) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=1005760) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 56583900551078019099084402098453953895796854085613907641584315463712743245310 None
Another command (pid=526712) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=364070) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=444480) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 100741046277976698091355461881278957289129483574699295401059627724112568351952 None
Another command (pid=693598) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=585221) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=580797) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 54467816699957310868315501683214961566651667885838211023479985920807039137951 None
Another command (pid=746016) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=735959) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=693148) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 21954638801068936504034210118077953754841741855184855014379533202806023700909 None
---- STDERR ----
Another command (pid=357211) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 89042802488602618375604280355334350636149332065849964000661663612401101599471 None
Another command (pid=371845) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=471380) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=375937) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 44029070711822732153235593010122611192624947286924936023580453596949378693334 None
---- STDERR ----
Another command (pid=360434) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 16321933437887742505141390927579738653815230835594321644502277410185901237196 None
Another command (pid=690978) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=595886) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=595894) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 59895376218697276425167521694114878671823596230269265814759679911056802092222 None
---- STDERR ----
Another command (pid=419597) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=409828) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 18464391388698791912176498599373566209086770634351664844545445188686654873182 None
Another command (pid=595886) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=601523) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=575472) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 34382942301929425820508009379047784321296369187303494933762826791096184130094 None
Another command (pid=688303) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=693598) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=585221) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 71148041365496031312751160228705723016150469688209236682027007412970262191219 None
Another command (pid=526712) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=380014) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=444480) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 106428166288464941344938838942807451204309403128748994130461565745102631722864 None
Another command (pid=357211) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=364070) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=444480) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 82148981450584922488978838715265993091778245014998080555188568883766036519326 None
Another command (pid=444480) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=434728) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=371845) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 35430947440920384317227825638555361699550459157393950226355431689992694365692 None
Another command (pid=357211) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=364070) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=444480) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 88198270142052281380969767981660991935607319254828914434852925739627224399046 None
Another command (pid=600643) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=716357) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=565192) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 8553317508735391547021898572167663183254408697843438411441134471319028523514 None
---- STDERR ----
Another command (pid=357211) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=526712) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 103708030891897776394784946726555833418776018972557263080538046142596414341756 None
Another command (pid=471380) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=375937) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=541444) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 19229005025842122006920339477153379558607404741603620520525841742737743456241 None
Another command (pid=578830) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=370211) is running. Waiting for it to complete on the server (server_pid=237102)...
Another command (pid=690978) is running. Waiting for it to complete on the server (server_pid=237102)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 13112744327490632752315992170318007739743633020074362557123742898781074616987 332
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 15349178964447310782368204898509377966873939788239073116383286817193071498210 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 11965420581333689755487962690565779981169875645268386158061514594696361932899 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 100227510325612085029704119972284631974727228931194131443482539603940535079605 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 92876478089365771934758909523351261126251383881517874243817103400440708237686 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 13261857017957115599014079513831066223994117791963624431672161768501001895391 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 68717602059234963591479897877858421090075785762065199166473444959440670207319 366
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 39353219335450032412505067320330016047236622679267285597482198108842778603548 366
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 48159679224882062640339624213269632005479651866013301389781709870655210319029 364
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 82576745713778170017235739194096736870903026137427188661479809516190943278151 326
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 81115572513428400217229903018340801440096924241371734422288146015334244921898 326
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 114378197251454548425647712100715389956385555415566926931401611264267602082113 327
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 28432833676073212414389060866034212798326014664377484813389962689670186703053 326
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 80865332738242563803916244221288290832560899364119626613662904131739624510959 325
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 112362676849183235719138058519446198316089544689123027416099406742721401026984 326
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 17422803063802265089471264008224444673841676618796787108242282164786378549064 321
UVM_ERROR @ 3384.494088 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3384.494088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 10932588955362963183651239334853519752560161703214824199379657936714146276445 312
UVM_ERROR @ 3487.662602 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3487.662602 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 2 test runs
chip_sw_lc_walkthrough_prod 3524507641591609024245786566886932256166905906504399274936845291750169660053 369
UVM_INFO @ 9243.936661 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 114267362661235276769255748681744926794769969672604465578046355988102581810285 341
UVM_INFO @ 6379.862031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 2 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1662090158377709612996465507831824842367952376213824268185296479480690028541 344
UVM_ERROR @ 13231.412500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13231.412500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 96920254276432209787252112371432697682378681926524969867278953074571906740986 330
UVM_ERROR @ 8635.300000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8635.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 86624274597185590910529610140126004321328648760287807503747228467514821335233 318
UVM_ERROR @ 2877.628088 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2877.628088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 56519294177806830507504485132343984871507250770504636958127450113061430653241 315
UVM_ERROR @ 4043.548091 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 4043.548091 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 76931784384153942483472384607005659294147427197699645607657400754213587021747 222
TL item was: req: (cip_tl_seq_item@33004) { a_addr: 'h10698 a_data: 'hec978bb6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h19e41 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2365.045792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 70224287078128146034345835545313916974746047223931396395496635814101735841705 224
TL item was: req: (cip_tl_seq_item@31822) { a_addr: 'h104f8 a_data: 'h5e589b4c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h1a56d d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2380.095283 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 49091449959794851465683463699225204415698058387936061959878843723597313390049 367
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 63002070659551158625777739818054627293974640499284906915759427294893831803595 325
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 34414553958888915589101590898898164982977745405829125695992838005080378788486 366
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 35206764179897480490083610572864886626842489570418696055166711102862111022335 325
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] 1 test run
chip_sw_sleep_pin_mio_dio_val 95143185036465386273222641499958622698696830701377990793559265599708976437691 456
UVM_INFO @ 3197.576500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 54862627356495397911567975787374591479913955846976934580312005022648231077619 325
UVM_INFO @ 3408.464327 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 65114075971441912072410721912466210636073211795987389218523182986706252532455 314
UVM_INFO @ 2963.251704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 65755839939425847295914979948356264355345748232736565136158889846012994144872 347
UVM_INFO @ 6712.780588 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 36447624687384813600829674460504481342831537055337278252345724950926368454147 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_dev 63169844757716755067454522611386392609262399338986468676502560662903142390089 308
UVM_INFO @ 26318.812521 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 4704878255037411422121526245398694742293077734201608675216169606223226109650 308
UVM_ERROR @ 3218.866754 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 3218.866754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 1415563051685828946843244904417659647029949510812458819237958244281979056804 332
UVM_INFO @ 34166.301821 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 20372103617191402033542960593820251545598321226034649012654202977077941326438 312
UVM_INFO @ 3166.257512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 19353365681084421199441798562599549577343584205460233816853640806256130239620 308
UVM_INFO @ 2562.432840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 30340962307150567709108753609819106307828263742226371100159238526844985858151 None
Offending '(reset_cause == HwReq)' 1 test run
chip_sw_sensor_ctrl_alert 93686052310112014259708709145094258457410242121913943969621437122954969113867 321
UVM_ERROR @ 2824.310544 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2824.310544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 100429722426391677805097426752686181485352994231347694240101846825205231975011 343
UVM_INFO @ 3344.588245 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 56710429763978723013790827131385070056553287613079280089804484283533627026700 256
UVM_INFO @ 5747.212955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 58749484508139726937780155924294236195298539669366179136134739851387633613991 317
UVM_INFO @ 3326.766500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 79764615942255596125857375370610581075604252738690611116897996549842046075627 323
UVM_INFO @ 3575.332000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 8083583226535999840442679479434414629803076601487249520255992021735134155177 327
UVM_INFO @ 12471.009534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 109491405018396939425161682320594092578551629083919803423373070610093832936748 272
UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 47363888905693041423932486547413890227851865408951842122455491823641600907212 325
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 13895162160773804359065202011992388384798389649399194904440462536547221973445 328
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! 1 test run
rom_e2e_jtag_debug_test_unlocked0 98629996638261038017392102644034312497632178641965259878365806087981327973932 330
UVM_INFO @ 14807.585310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 71909110790793311469452575505806168622199809935236309182278687877531901412047 319
UVM_INFO @ 17187.834980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 103055704240652796308709697253557106181142644257629187351032565645076334215951 332
UVM_ERROR @ 5156.771169 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5156.771169 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---