Simulation Results: clkmgr

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.18 %
  • code
  • 97.58 %
  • assert
  • 94.92 %
  • func
  • 84.05 %
  • line
  • 98.19 %
  • branch
  • 97.91 %
  • cond
  • 92.61 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.880s 64.628us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.710s 18.862us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.770s 32.419us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 16.760s 6803.681us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.260s 28.033us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.440s 131.708us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.770s 32.419us 1 1 100.00
clkmgr_csr_aliasing 1.260s 28.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.730s 25.689us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.060s 25.421us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.950s 40.004us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.890s 22.786us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.880s 64.628us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 3.700s 682.359us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 4.510s 1537.198us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 3.700s 682.359us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 8.680s 1988.087us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.930s 44.357us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.430s 320.918us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.430s 320.918us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.710s 18.862us 1 1 100.00
clkmgr_csr_rw 0.770s 32.419us 1 1 100.00
clkmgr_csr_aliasing 1.260s 28.033us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 29.934us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.710s 18.862us 1 1 100.00
clkmgr_csr_rw 0.770s 32.419us 1 1 100.00
clkmgr_csr_aliasing 1.260s 28.033us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 29.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 24.450s 10187.185us 0 1 0.00
clkmgr_tl_intg_err 1.460s 110.217us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 73.536us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 73.536us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 73.536us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 73.536us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.910s 252.077us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.460s 110.217us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 3.700s 682.359us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 4.510s 1537.198us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.270s 73.536us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.070s 587.045us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.910s 81.259us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.040s 28.163us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.910s 68.302us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.880s 56.195us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.770s 32.419us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 24.450s 10187.185us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 32.419us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 32.419us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 24.450s 10187.185us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.190s 193.815us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 11.870s 1407.553us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1030) [clkmgr_common_vseq] timeout wait for alert handshake:fatal_fault 1 test run
clkmgr_sec_cm 110160550005237210366473855666554444703456024718451807674257142932853341432293 126
UVM_INFO @ 10187185087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---