Simulation Results: edn/edn0

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.36 %
  • code
  • 86.51 %
  • assert
  • 97.61 %
  • func
  • 80.95 %
  • line
  • 98.59 %
  • branch
  • 95.54 %
  • cond
  • 89.55 %
  • toggle
  • 94.58 %
  • FSM
  • 54.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.960s 21.063us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.910s 33.908us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.940s 14.264us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.710s 135.006us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.530s 304.628us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.900s 61.733us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.940s 14.264us 1 1 100.00
edn_csr_aliasing 1.530s 304.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.090s 105.095us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.090s 105.095us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.090s 105.095us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.940s 23.108us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.210s 135.775us 1 1 100.00
errs 1 1 100.00
edn_err 0.770s 50.025us 1 1 100.00
disable 2 2 100.00
edn_disable 0.990s 32.226us 1 1 100.00
edn_disable_auto_req_mode 1.270s 96.986us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.440s 522.961us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 19.046us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 66.972us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.980s 40.510us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.980s 40.510us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.910s 33.908us 1 1 100.00
edn_csr_rw 0.940s 14.264us 1 1 100.00
edn_csr_aliasing 1.530s 304.628us 1 1 100.00
edn_same_csr_outstanding 1.140s 30.160us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.910s 33.908us 1 1 100.00
edn_csr_rw 0.940s 14.264us 1 1 100.00
edn_csr_aliasing 1.530s 304.628us 1 1 100.00
edn_same_csr_outstanding 1.140s 30.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.790s 945.329us 1 1 100.00
edn_tl_intg_err 1.360s 53.051us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 51.382us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.210s 135.775us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.790s 945.329us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.790s 945.329us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.790s 945.329us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.790s 945.329us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.210s 135.775us 1 1 100.00
edn_sec_cm 5.790s 945.329us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.210s 135.775us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.360s 53.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 52.650s 6054.161us 1 1 100.00