Simulation Results: edn/edn1

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.41 %
  • code
  • 82.95 %
  • assert
  • 96.88 %
  • func
  • 79.41 %
  • line
  • 98.25 %
  • branch
  • 93.72 %
  • cond
  • 91.08 %
  • toggle
  • 87.36 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.870s 47.481us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.070s 168.512us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.780s 51.225us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.180s 983.084us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.880s 82.877us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.390s 68.509us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.780s 51.225us 1 1 100.00
edn_csr_aliasing 0.880s 82.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.170s 33.200us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.170s 33.200us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.170s 33.200us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.980s 23.474us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.110s 31.773us 1 1 100.00
errs 1 1 100.00
edn_err 0.830s 29.003us 1 1 100.00
disable 2 2 100.00
edn_disable 0.750s 32.598us 1 1 100.00
edn_disable_auto_req_mode 0.970s 104.372us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.480s 758.118us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.770s 24.842us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.980s 56.719us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.810s 240.978us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.810s 240.978us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.070s 168.512us 1 1 100.00
edn_csr_rw 0.780s 51.225us 1 1 100.00
edn_csr_aliasing 0.880s 82.877us 1 1 100.00
edn_same_csr_outstanding 1.140s 245.244us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.070s 168.512us 1 1 100.00
edn_csr_rw 0.780s 51.225us 1 1 100.00
edn_csr_aliasing 0.880s 82.877us 1 1 100.00
edn_same_csr_outstanding 1.140s 245.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.190s 657.293us 1 1 100.00
edn_tl_intg_err 1.220s 60.999us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.950s 18.648us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.110s 31.773us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.190s 657.293us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.190s 657.293us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.190s 657.293us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.190s 657.293us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.110s 31.773us 1 1 100.00
edn_sec_cm 2.190s 657.293us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.110s 31.773us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.220s 60.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 52.220s 25315.083us 1 1 100.00