Simulation Results: flash_ctrl

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.63 %
  • code
  • 94.33 %
  • assert
  • 96.76 %
  • func
  • 95.79 %
  • line
  • 95.98 %
  • branch
  • 97.10 %
  • cond
  • 93.82 %
  • toggle
  • 98.36 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
98.28%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 20.070s 21.701us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 8.340s 182.738us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 9.500s 55.048us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 6.840s 154.190us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 35.910s 2639.499us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 38.740s 6243.429us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.610s 376.773us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 6.840s 154.190us 1 1 100.00
flash_ctrl_csr_aliasing 38.740s 6243.429us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.340s 17.587us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.320s 18.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.860s 39.419us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 14.060s 160.751us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1141.420s 83820.406us 1 1 100.00
flash_ctrl_hw_rma_reset 547.190s 60135.402us 1 1 100.00
flash_ctrl_lcmgr_intg 5.360s 106.127us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1562.520s 1226829.532us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 170.890s 2911.062us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.310s 36.716us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1788.160s 98666.817us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 42.370s 1446.858us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 11.300s 40.519us 1 1 100.00
flash_ctrl_rw_evict_all_en 12.680s 29.536us 1 1 100.00
flash_ctrl_re_evict 12.940s 222.493us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 91.660s 749.275us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 91.660s 749.275us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 305.920s 10490.741us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.750s 550.842us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 336.260s 153.240us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 403.470s 13025.482us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 269.460s 4074.894us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 840.320s 620.448us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.480s 41.308us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 137.550s 1637.573us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 7.670s 66.502us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.610s 28.216us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 702.600s 626.028us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 108.060s 12475.150us 1 1 100.00
flash_ctrl_otp_reset 50.290s 90.191us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1141.420s 83820.406us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 81.260s 5509.109us 1 1 100.00
flash_ctrl_intr_wr 45.500s 2654.015us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 225.090s 164844.480us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 134.550s 52966.681us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 40.980s 8180.787us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 32.370s 1680.597us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.260s 26.723us 1 1 100.00
flash_ctrl_ro_derr 69.140s 589.726us 1 1 100.00
flash_ctrl_rw_derr 148.510s 4092.906us 1 1 100.00
flash_ctrl_derr_detect 100.130s 3243.959us 1 1 100.00
flash_ctrl_integrity 405.660s 45506.035us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.400s 126.651us 1 1 100.00
flash_ctrl_ro_serr 65.260s 650.698us 1 1 100.00
flash_ctrl_rw_serr 118.400s 7908.147us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 51.670s 1630.160us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 64.000s 2263.254us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 164.710s 12997.916us 1 1 100.00
flash_ctrl_write_word_sweep 6.100s 78.835us 1 1 100.00
flash_ctrl_read_word_sweep 5.630s 26.625us 1 1 100.00
flash_ctrl_ro 71.860s 1312.119us 1 1 100.00
flash_ctrl_rw 3603.635s 0.000us 0 1 0.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.270s 700.718us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 555.410s 160780.865us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 13.780s 10236.130us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.540s 53.605us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.100s 31.203us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.180s 224.983us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.180s 224.983us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 9.500s 55.048us 1 1 100.00
flash_ctrl_csr_rw 6.840s 154.190us 1 1 100.00
flash_ctrl_csr_aliasing 38.740s 6243.429us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.420s 181.803us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 9.500s 55.048us 1 1 100.00
flash_ctrl_csr_rw 6.840s 154.190us 1 1 100.00
flash_ctrl_csr_aliasing 38.740s 6243.429us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.420s 181.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 11.490s 89.729us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 11.490s 89.729us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 11.490s 89.729us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 11.490s 89.729us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 26.050s 91.293us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1572.810s 11070.426us 1 1 100.00
flash_ctrl_tl_intg_err 336.840s 2845.209us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 336.840s 2845.209us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 336.840s 2845.209us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 13.660s 142.966us 1 1 100.00
flash_ctrl_wr_intg 5.740s 363.480us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 20.070s 21.701us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 50.290s 90.191us 1 1 100.00
flash_ctrl_disable 7.670s 66.502us 1 1 100.00
flash_ctrl_sec_info_access 40.670s 4090.750us 1 1 100.00
flash_ctrl_connect 6.610s 28.216us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.530s 77.603us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.840s 154.190us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 11.490s 89.729us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.840s 154.190us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 11.490s 89.729us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.840s 154.190us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 11.490s 89.729us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 7.670s 66.502us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 13.660s 142.966us 1 1 100.00
flash_ctrl_access_after_disable 5.550s 19.548us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.040s 89.462us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 7.670s 66.502us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.750s 550.842us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
flash_ctrl_rw 3603.635s 0.000us 0 1 0.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 118.400s 7908.147us 1 1 100.00
flash_ctrl_rw_derr 148.510s 4092.906us 1 1 100.00
flash_ctrl_integrity 405.660s 45506.035us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1141.420s 83820.406us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1572.810s 11070.426us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1572.810s 11070.426us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1572.810s 11070.426us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1572.810s 11070.426us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 7.740s 941.505us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 5.670s 76.437us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.040s 53.011us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1572.810s 11070.426us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1572.810s 11070.426us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1572.810s 11070.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 16.880s 143.018us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 176.270s 7469.510us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
flash_ctrl_rw 40366727321278659422299860784059197794671708471154046070491300864451712874838 None