Simulation Results: hmac

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.90 %
  • code
  • 96.24 %
  • assert
  • 97.14 %
  • func
  • 43.32 %
  • line
  • 99.12 %
  • branch
  • 97.85 %
  • cond
  • 96.01 %
  • toggle
  • 100.00 %
  • FSM
  • 88.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.950s 1386.427us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.760s 17.512us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.790s 18.741us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.770s 2028.117us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.230s 213.866us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.980s 26.734us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.790s 18.741us 1 1 100.00
hmac_csr_aliasing 2.230s 213.866us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 2.090s 2654.646us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 14.970s 334.907us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 196.030s 19550.194us 1 1 100.00
hmac_test_sha384_vectors 336.630s 10795.332us 1 1 100.00
hmac_test_sha512_vectors 424.180s 27958.467us 1 1 100.00
hmac_test_hmac256_vectors 4.970s 600.347us 1 1 100.00
hmac_test_hmac384_vectors 9.390s 1403.374us 1 1 100.00
hmac_test_hmac512_vectors 9.970s 310.798us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 14.350s 1575.079us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 672.810s 11531.572us 1 1 100.00
error 1 1 100.00
hmac_error 51.120s 15298.987us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 26.600s 3249.006us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.950s 1386.427us 1 1 100.00
hmac_long_msg 2.090s 2654.646us 1 1 100.00
hmac_back_pressure 14.970s 334.907us 1 1 100.00
hmac_datapath_stress 672.810s 11531.572us 1 1 100.00
hmac_burst_wr 14.350s 1575.079us 1 1 100.00
hmac_stress_all 363.860s 40230.276us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.950s 1386.427us 1 1 100.00
hmac_long_msg 2.090s 2654.646us 1 1 100.00
hmac_back_pressure 14.970s 334.907us 1 1 100.00
hmac_datapath_stress 672.810s 11531.572us 1 1 100.00
hmac_wipe_secret 26.600s 3249.006us 1 1 100.00
hmac_test_sha256_vectors 196.030s 19550.194us 1 1 100.00
hmac_test_sha384_vectors 336.630s 10795.332us 1 1 100.00
hmac_test_sha512_vectors 424.180s 27958.467us 1 1 100.00
hmac_test_hmac256_vectors 4.970s 600.347us 1 1 100.00
hmac_test_hmac384_vectors 9.390s 1403.374us 1 1 100.00
hmac_test_hmac512_vectors 9.970s 310.798us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.950s 1386.427us 1 1 100.00
hmac_long_msg 2.090s 2654.646us 1 1 100.00
hmac_back_pressure 14.970s 334.907us 1 1 100.00
hmac_datapath_stress 672.810s 11531.572us 1 1 100.00
hmac_burst_wr 14.350s 1575.079us 1 1 100.00
hmac_error 51.120s 15298.987us 1 1 100.00
hmac_wipe_secret 26.600s 3249.006us 1 1 100.00
hmac_test_sha256_vectors 196.030s 19550.194us 1 1 100.00
hmac_test_sha384_vectors 336.630s 10795.332us 1 1 100.00
hmac_test_sha512_vectors 424.180s 27958.467us 1 1 100.00
hmac_test_hmac256_vectors 4.970s 600.347us 1 1 100.00
hmac_test_hmac384_vectors 9.390s 1403.374us 1 1 100.00
hmac_test_hmac512_vectors 9.970s 310.798us 1 1 100.00
hmac_stress_all 363.860s 40230.276us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 363.860s 40230.276us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.560s 20.195us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 13.114us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.140s 55.450us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.140s 55.450us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.760s 17.512us 1 1 100.00
hmac_csr_rw 0.790s 18.741us 1 1 100.00
hmac_csr_aliasing 2.230s 213.866us 1 1 100.00
hmac_same_csr_outstanding 0.950s 24.676us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.760s 17.512us 1 1 100.00
hmac_csr_rw 0.790s 18.741us 1 1 100.00
hmac_csr_aliasing 2.230s 213.866us 1 1 100.00
hmac_same_csr_outstanding 0.950s 24.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.740s 83.698us 1 1 100.00
hmac_tl_intg_err 2.310s 829.023us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.310s 829.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.950s 1386.427us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.130s 1318.735us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 22.280s 7965.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.790s 435.154us 1 1 100.00