Simulation Results: i2c

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.56 %
  • code
  • 81.45 %
  • assert
  • 96.19 %
  • func
  • 82.03 %
  • line
  • 96.38 %
  • branch
  • 92.26 %
  • cond
  • 84.89 %
  • toggle
  • 89.66 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 20.170s 2128.268us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 7.690s 1997.950us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.660s 40.300us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.720s 38.673us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.030s 191.073us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.020s 32.477us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.840s 142.326us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.720s 38.673us 1 1 100.00
i2c_csr_aliasing 1.020s 32.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.800s 24.753us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 1605.670s 93508.020us 0 1 0.00
host_maxperf 0 1 0.00
i2c_host_perf 1.080s 539.216us 0 1 0.00
host_override 1 1 100.00
i2c_host_override 0.640s 52.960us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 129.730s 3575.734us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 43.820s 6646.943us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.820s 72.568us 1 1 100.00
i2c_host_fifo_fmt_empty 4.270s 378.609us 1 1 100.00
i2c_host_fifo_reset_rx 2.470s 691.735us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 86.780s 5124.753us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 5.040s 462.162us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.380s 429.672us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.040s 4138.979us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 55.620s 49392.373us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.270s 1950.735us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 33.860s 2499.750us 1 1 100.00
i2c_target_intr_smoke 4.690s 2492.717us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.050s 237.098us 1 1 100.00
i2c_target_fifo_reset_tx 0.930s 191.240us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 115.980s 41201.878us 1 1 100.00
i2c_target_stress_rd 33.860s 2499.750us 1 1 100.00
i2c_target_intr_stress_wr 14.010s 8308.220us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 3.920s 4288.025us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 8.840s 3514.852us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.210s 1465.182us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 18.430s 10062.221us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.680s 385.516us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.860s 2246.931us 1 1 100.00
host_mode_config_perf 1 2 50.00
i2c_host_perf 1.080s 539.216us 0 1 0.00
i2c_host_perf_precise 3.600s 286.402us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 5.040s 462.162us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.350s 95.038us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.680s 867.795us 1 1 100.00
i2c_target_nack_acqfull_addr 1.640s 1978.709us 1 1 100.00
i2c_target_nack_txstretch 1.030s 545.803us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 8.840s 1409.377us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.470s 517.022us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.660s 52.757us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.660s 19.869us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.170s 108.658us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.170s 108.658us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.660s 40.300us 1 1 100.00
i2c_csr_rw 0.720s 38.673us 1 1 100.00
i2c_csr_aliasing 1.020s 32.477us 1 1 100.00
i2c_same_csr_outstanding 0.980s 184.731us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.660s 40.300us 1 1 100.00
i2c_csr_rw 0.720s 38.673us 1 1 100.00
i2c_csr_aliasing 1.020s 32.477us 1 1 100.00
i2c_same_csr_outstanding 0.980s 184.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.670s 539.474us 1 1 100.00
i2c_sec_cm 0.790s 52.488us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.670s 539.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 1.480s 112.762us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.680s 28.830us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 16.440s 690.800us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 2 test runs
i2c_host_stress_all 89150699028825480528802575870221614920812939367659616407694625205378726876080 166
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @24384780
i2c_host_mode_toggle 1474477291529392950559587465741731147195236710494737519715678540486042877610 90
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13057
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 34873839852658606546742307961969575607677809468008030715019039212082389856875 97
UVM_INFO @ 112762237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 94495736895271338013565081727687847077490635626968171877369020258102569856055 95
UVM_INFO @ 690799950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead 1 test run
i2c_host_perf 36670748890783238713058157545821218223382690975004301645228056808727661927753 87
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 1 test run
i2c_host_error_intr 71496003158037037648120457396075103629577695456452289797989350339158525930874 109
UVM_INFO @ 24753297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 100804502339941464517677509340550475976760105059370538796776697031199233139229 89
UVM_INFO @ 4138978648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 22065801835258066291789106012833816691385251419072672375685263451928237533341 83
UVM_INFO @ 28830400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 14073608943832619407805862736925616003824672931038904361369208887537472582122 84
UVM_INFO @ 10062221188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---