Simulation Results: keymgr

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.48 %
  • code
  • 95.11 %
  • assert
  • 96.80 %
  • func
  • 58.52 %
  • line
  • 98.84 %
  • branch
  • 97.81 %
  • cond
  • 93.28 %
  • toggle
  • 97.27 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.730s 128.898us 1 1 100.00
random 1 1 100.00
keymgr_random 2.160s 50.234us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.860s 111.121us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.080s 23.057us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 4.110s 133.949us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 6.120s 726.493us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.190s 330.853us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.080s 23.057us 1 1 100.00
keymgr_csr_aliasing 6.120s 726.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 2.770s 61.229us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 3.900s 602.054us 1 1 100.00
keymgr_sideload_kmac 2.310s 274.142us 1 1 100.00
keymgr_sideload_aes 5.780s 495.904us 1 1 100.00
keymgr_sideload_otbn 2.110s 507.876us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.880s 267.849us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 5.460s 481.106us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 1.630s 30.042us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 2.680s 125.437us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.530s 114.439us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.360s 93.743us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 140.670s 67023.214us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.680s 16.920us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.660s 12.483us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.100s 85.518us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.100s 85.518us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.860s 111.121us 1 1 100.00
keymgr_csr_rw 1.080s 23.057us 1 1 100.00
keymgr_csr_aliasing 6.120s 726.493us 1 1 100.00
keymgr_same_csr_outstanding 1.250s 45.942us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.860s 111.121us 1 1 100.00
keymgr_csr_rw 1.080s 23.057us 1 1 100.00
keymgr_csr_aliasing 6.120s 726.493us 1 1 100.00
keymgr_same_csr_outstanding 1.250s 45.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
keymgr_tl_intg_err 4.350s 1113.317us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.520s 116.740us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.520s 116.740us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.520s 116.740us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.520s 116.740us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 2.920s 304.813us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 4.350s 1113.317us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.520s 116.740us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 2.770s 61.229us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.160s 50.234us 1 1 100.00
keymgr_csr_rw 1.080s 23.057us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.160s 50.234us 1 1 100.00
keymgr_csr_rw 1.080s 23.057us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.160s 50.234us 1 1 100.00
keymgr_csr_rw 1.080s 23.057us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 5.460s 481.106us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.530s 114.439us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.530s 114.439us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.160s 50.234us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.660s 101.826us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.620s 448.617us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 5.460s 481.106us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.620s 448.617us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.620s 448.617us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.620s 448.617us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 11.010s 1107.265us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.620s 448.617us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 4.490s 916.582us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 26228261815508709656170623425352575959553542860710899238231994744501691421296 391
UVM_INFO @ 916581855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---