Simulation Results: kmac/unmasked

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.41 %
  • code
  • 87.86 %
  • assert
  • 97.75 %
  • func
  • 91.63 %
  • line
  • 97.30 %
  • branch
  • 95.28 %
  • cond
  • 93.99 %
  • toggle
  • 99.83 %
  • FSM
  • 52.89 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 20.760s 6161.248us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.860s 56.746us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.910s 26.206us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 13.380s 1516.762us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.390s 530.166us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.790s 316.392us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.910s 26.206us 1 1 100.00
kmac_csr_aliasing 3.390s 530.166us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.630s 37.165us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 0.950s 37.464us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 410.870s 14228.381us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 292.540s 4917.090us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 2078.040s 404457.157us 1 1 100.00
kmac_test_vectors_sha3_256 31.260s 2424.796us 1 1 100.00
kmac_test_vectors_sha3_384 18.360s 7682.905us 1 1 100.00
kmac_test_vectors_sha3_512 10.520s 727.531us 1 1 100.00
kmac_test_vectors_shake_128 124.760s 3607.419us 1 1 100.00
kmac_test_vectors_shake_256 219.790s 38969.124us 1 1 100.00
kmac_test_vectors_kmac 1.730s 119.495us 1 1 100.00
kmac_test_vectors_kmac_xof 1.640s 328.260us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 55.980s 5094.604us 1 1 100.00
app 1 1 100.00
kmac_app 195.400s 34804.189us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 85.840s 20215.360us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 47.010s 1804.372us 1 1 100.00
error 1 1 100.00
kmac_error 117.060s 31324.875us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 3.170s 966.339us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 28.790s 10025.295us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 20.150s 2531.859us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 4.580s 976.366us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 23.750s 4648.212us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 10.040s 2369.735us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 105.500s 2234.120us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.690s 42.805us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.720s 20.019us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.800s 364.913us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.800s 364.913us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.860s 56.746us 1 1 100.00
kmac_csr_rw 0.910s 26.206us 1 1 100.00
kmac_csr_aliasing 3.390s 530.166us 1 1 100.00
kmac_same_csr_outstanding 1.160s 99.942us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.860s 56.746us 1 1 100.00
kmac_csr_rw 0.910s 26.206us 1 1 100.00
kmac_csr_aliasing 3.390s 530.166us 1 1 100.00
kmac_same_csr_outstanding 1.160s 99.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.450s 77.722us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.450s 77.722us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.450s 77.722us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.450s 77.722us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 1.690s 56.857us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 43.060s 5674.572us 1 1 100.00
kmac_tl_intg_err 2.360s 2939.715us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.360s 2939.715us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 10.040s 2369.735us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 20.760s 6161.248us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 55.980s 5094.604us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.450s 77.722us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 43.060s 5674.572us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 43.060s 5674.572us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 43.060s 5674.572us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 20.760s 6161.248us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 10.040s 2369.735us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 43.060s 5674.572us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 179.920s 50395.570us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 20.760s 6161.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 85.560s 7902.561us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 1 test run
kmac_sideload_invalid 102501546947509775860244404030790987768308010561956476841401227622623328383280 83
UVM_INFO @ 10025295319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---