Simulation Results: lc_ctrl/volatile_unlock_disabled

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.89 %
  • code
  • 84.78 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.19 %
  • branch
  • 93.85 %
  • cond
  • 79.52 %
  • toggle
  • 88.85 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.370s 57.056us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.720s 216.214us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.710s 40.945us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.830s 345.796us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.460s 40.116us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.800s 67.350us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.710s 40.945us 1 1 100.00
lc_ctrl_csr_aliasing 1.460s 40.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.810s 402.803us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.950s 4542.207us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.730s 39.648us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.360s 37.693us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.230s 3765.408us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_ctrl_prog_failure 1.360s 37.693us 1 1 100.00
lc_ctrl_errors 4.230s 3765.408us 1 1 100.00
lc_ctrl_security_escalation 3.800s 271.947us 1 1 100.00
lc_ctrl_jtag_state_failure 31.390s 1609.639us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.290s 1813.526us 1 1 100.00
lc_ctrl_jtag_errors 16.150s 2444.120us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.150s 196.369us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.560s 329.426us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.290s 1813.526us 1 1 100.00
lc_ctrl_jtag_errors 16.150s 2444.120us 1 1 100.00
lc_ctrl_jtag_access 2.570s 306.822us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.360s 1044.069us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.100s 994.377us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.100s 87.142us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.490s 3565.062us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.540s 2887.147us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.190s 22.266us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.660s 229.908us 1 1 100.00
lc_ctrl_jtag_alert_test 0.900s 64.266us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.160s 203.526us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.820s 183.519us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 160.940s 15886.387us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.740s 32.131us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.700s 212.423us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.700s 212.423us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.720s 216.214us 1 1 100.00
lc_ctrl_csr_rw 0.710s 40.945us 1 1 100.00
lc_ctrl_csr_aliasing 1.460s 40.116us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 385.106us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.720s 216.214us 1 1 100.00
lc_ctrl_csr_rw 0.710s 40.945us 1 1 100.00
lc_ctrl_csr_aliasing 1.460s 40.116us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 385.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.490s 239.522us 1 1 100.00
lc_ctrl_tl_intg_err 1.630s 245.888us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.630s 245.888us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.950s 4542.207us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_ctrl_sec_cm 5.490s 239.522us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_ctrl_sec_cm 5.490s 239.522us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_ctrl_sec_cm 5.490s 239.522us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_ctrl_sec_cm 5.490s 239.522us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_ctrl_sec_cm 5.490s 239.522us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_ctrl_sec_cm 5.490s 239.522us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_ctrl_sec_cm 5.490s 239.522us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.320s 666.248us 1 1 100.00
lc_ctrl_sec_cm 5.490s 239.522us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.800s 271.947us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.810s 402.803us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.560s 329.426us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.500s 302.695us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.500s 302.695us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.370s 766.257us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.390s 790.232us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.390s 790.232us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 70.300s 7337.411us 1 1 100.00