Simulation Results: lc_ctrl/volatile_unlock_enabled

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.66 %
  • code
  • 84.08 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 79.01 %
  • toggle
  • 86.41 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.820s 80.999us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.830s 51.697us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.790s 44.775us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.030s 41.114us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 33.305us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.020s 21.835us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.790s 44.775us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 33.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.710s 360.181us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.800s 309.009us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.820s 23.158us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.050s 230.747us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.770s 407.322us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_ctrl_prog_failure 2.050s 230.747us 1 1 100.00
lc_ctrl_errors 7.770s 407.322us 1 1 100.00
lc_ctrl_security_escalation 6.670s 603.388us 1 1 100.00
lc_ctrl_jtag_state_failure 18.250s 7367.703us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.010s 1307.453us 1 1 100.00
lc_ctrl_jtag_errors 45.770s 10548.862us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.750s 166.098us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.290s 391.283us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.010s 1307.453us 1 1 100.00
lc_ctrl_jtag_errors 45.770s 10548.862us 1 1 100.00
lc_ctrl_jtag_access 4.600s 1022.943us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.110s 1354.359us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.020s 603.284us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.840s 163.885us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.800s 1742.674us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.840s 425.870us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.110s 163.746us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.330s 369.928us 1 1 100.00
lc_ctrl_jtag_alert_test 1.440s 73.869us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.970s 464.330us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.910s 13.834us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 180.440s 62241.629us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.920s 21.166us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.590s 144.823us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.590s 144.823us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 51.697us 1 1 100.00
lc_ctrl_csr_rw 0.790s 44.775us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 33.305us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.160s 21.920us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 51.697us 1 1 100.00
lc_ctrl_csr_rw 0.790s 44.775us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 33.305us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.160s 21.920us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.560s 279.521us 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 466.813us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.790s 466.813us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.800s 309.009us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_ctrl_sec_cm 6.560s 279.521us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_ctrl_sec_cm 6.560s 279.521us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_ctrl_sec_cm 6.560s 279.521us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_ctrl_sec_cm 6.560s 279.521us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_ctrl_sec_cm 6.560s 279.521us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_ctrl_sec_cm 6.560s 279.521us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_ctrl_sec_cm 6.560s 279.521us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.080s 285.272us 1 1 100.00
lc_ctrl_sec_cm 6.560s 279.521us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.670s 603.388us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.710s 360.181us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.290s 391.283us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.670s 2767.215us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.670s 2767.215us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.850s 268.684us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.060s 341.477us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.060s 341.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 42.190s 14185.971us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 1 test run
lc_ctrl_stress_all_with_rand_reset 14638072257596212193813944615560044198892446835158674464643733563323739229601 6955
UVM_INFO @ 14185970580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---