Simulation Results: otbn

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.28 %
  • code
  • 94.26 %
  • assert
  • 89.38 %
  • func
  • 96.19 %
  • block
  • 99.33 %
  • line
  • 99.49 %
  • branch
  • 91.40 %
  • toggle
  • 88.59 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
85.71%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 76.211us 1 1 100.00
single_binary 1 1 100.00
otbn_single 10.000s 229.926us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 40.117us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 50.300us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 195.404us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 18.695us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 4.000s 122.731us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 50.300us 1 1 100.00
otbn_csr_aliasing 5.000s 18.695us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 53.000s 4304.910us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 24.000s 3748.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 26.000s 266.062us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 29.000s 239.016us 0 1 0.00
back_to_back 0 1 0.00
otbn_multi 3.258s 0.000us 0 1 0.00
stress_all 1 1 100.00
otbn_stress_all 98.000s 520.729us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 27.037us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 25.095us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 54.430us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 9.000s 17.842us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 15.903us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 50.138us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 50.138us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 40.117us 1 1 100.00
otbn_csr_rw 3.000s 50.300us 1 1 100.00
otbn_csr_aliasing 5.000s 18.695us 1 1 100.00
otbn_same_csr_outstanding 4.000s 26.276us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 40.117us 1 1 100.00
otbn_csr_rw 3.000s 50.300us 1 1 100.00
otbn_csr_aliasing 5.000s 18.695us 1 1 100.00
otbn_same_csr_outstanding 4.000s 26.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 35.321us 1 1 100.00
otbn_dmem_err 8.000s 37.590us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 10.000s 111.281us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 202.407us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 110.508us 1 1 100.00
otbn_urnd_err 9.000s 43.823us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 26.136us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 25.334us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 38.583us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
otbn_tl_intg_err 10.000s 276.061us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 3.000s 0.847us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 76.211us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 37.590us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 35.321us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 276.061us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 27.037us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 35.321us 1 1 100.00
otbn_dmem_err 8.000s 37.590us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 25.095us 1 1 100.00
otbn_illegal_mem_acc 4.000s 26.136us 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 10.000s 229.926us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 35.321us 1 1 100.00
otbn_dmem_err 8.000s 37.590us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 25.095us 1 1 100.00
otbn_illegal_mem_acc 4.000s 26.136us 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 27.037us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 35.321us 1 1 100.00
otbn_dmem_err 8.000s 37.590us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 25.095us 1 1 100.00
otbn_illegal_mem_acc 4.000s 26.136us 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 10.000s 229.926us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 16.233us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 22.925us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 42.000s 318.265us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 42.000s 318.265us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 34.999us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 0 1 0.00
otbn_rf_bignum_intg_err 8.000s 53.119us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 36.841us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 36.841us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 10.423us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 229.926us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 229.926us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 10.000s 229.926us 1 1 100.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 3.258s 0.000us 0 1 0.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 10.000s 229.926us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 10.000s 229.926us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 19.000s 61.522us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 10.000s 229.926us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 191.000s 5953.914us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 26.000s 111.862us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 44.745us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_multi 111155208921814398161932366934947136919825373843006243107478697761306501882527 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 39690800220569759986059260871807382826062370131043926702447813651061002138831 349
UVM_INFO @ 239015688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_rf_bignum_intg_err 7783709660556751296784567190747122581863738920429774684209171666143798935334 119
UVM_INFO @ 53119230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 22921214349786327720122109297204515262200471444291291393627316482139557572474 162
UVM_INFO @ 111862268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 85396834112682056453276536319008346788724244970362084966332417031400415956872 86
UVM_INFO @ 847126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---