Simulation Results: otp_ctrl

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.71 %
  • code
  • 77.23 %
  • assert
  • 93.73 %
  • func
  • 71.17 %
  • line
  • 88.49 %
  • branch
  • 82.93 %
  • cond
  • 89.91 %
  • toggle
  • 82.96 %
  • FSM
  • 41.84 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.330s 108.334us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.340s 1351.884us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.530s 270.393us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.350s 51.648us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.990s 268.104us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.060s 176.344us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.310s 282.809us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.350s 51.648us 1 1 100.00
otp_ctrl_csr_aliasing 4.060s 176.344us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.160s 142.833us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.120s 39.297us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 11.080s 2493.912us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.210s 152.279us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 22.150s 16801.832us 1 1 100.00
otp_ctrl_check_fail 2.300s 160.552us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.500s 266.773us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 4.050s 358.700us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 12.660s 1132.908us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 5.720s 572.945us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 13.720s 961.800us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.860s 371.570us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 38.140s 12332.173us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 37.260s 2273.447us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.120s 41.088us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.240s 88.628us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.680s 75.899us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.680s 75.899us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.530s 270.393us 1 1 100.00
otp_ctrl_csr_rw 1.350s 51.648us 1 1 100.00
otp_ctrl_csr_aliasing 4.060s 176.344us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.560s 134.631us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.530s 270.393us 1 1 100.00
otp_ctrl_csr_rw 1.350s 51.648us 1 1 100.00
otp_ctrl_csr_aliasing 4.060s 176.344us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.560s 134.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
otp_ctrl_tl_intg_err 12.460s 1309.961us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.460s 1309.961us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.340s 1351.884us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.340s 1351.884us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
otp_ctrl_macro_errs 2.860s 371.570us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
otp_ctrl_macro_errs 2.860s 371.570us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.010s 363.100us 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.210s 152.279us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 2.300s 160.552us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 4.050s 358.700us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 4.050s 358.700us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 4.050s 358.700us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 4.050s 358.700us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 4.050s 358.700us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.340s 1351.884us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 4.050s 358.700us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.340s 1351.884us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 113.690s 18905.554us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.500s 266.773us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.340s 1351.884us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.340s 1351.884us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.860s 371.570us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.310s 7332.585us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 34.550s 12137.351us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 495062572440989646494132689344342030679087445133116878724608470626518251535 2791
UVM_INFO @ 371570089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 60714931622699811477322851167517457912155547861005402014627215040969248389008 5697
UVM_INFO @ 12137350700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---