Simulation Results: pattgen

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.05 %
  • code
  • 98.79 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.37 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 170.300us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 32.790us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 20.634us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 62.214us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 97.803us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 31.313us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 20.634us 1 1 100.00
pattgen_csr_aliasing 2.000s 97.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 442.000s 87583.578us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 10.000s 2693.652us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 19.423us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 3.000s 683.349us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 11.661us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 15.803us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 320.034us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 320.034us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 32.790us 1 1 100.00
pattgen_csr_rw 1.000s 20.634us 1 1 100.00
pattgen_csr_aliasing 2.000s 97.803us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 14.460us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 32.790us 1 1 100.00
pattgen_csr_rw 1.000s 20.634us 1 1 100.00
pattgen_csr_aliasing 2.000s 97.803us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 14.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 276.260us 1 1 100.00
pattgen_sec_cm 1.000s 37.936us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 276.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 92.000s 10684.272us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 1.000s 33.672us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
pattgen_stress_all_with_rand_reset 22203275749485507467138751056502991574517231050188250975348543318556062051431 136
UVM_ERROR @ 247502089 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 247502089 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 247542905 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: 1 test run
pattgen_stress_all 75716700329414974848565790306081289572910205417892104425115100283158694056092 154
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Name Type Size Value
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exp_item pattgen_item - @11209