| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| pwm_smoke | 3.000s | 518.811us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pwm_csr_hw_reset | 1.000s | 49.073us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| pwm_csr_rw | 2.000s | 32.883us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pwm_csr_bit_bash | 3.000s | 362.224us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pwm_csr_aliasing | 1.000s | 68.217us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| pwm_csr_mem_rw_with_rand_reset | 1.000s | 26.004us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| pwm_csr_rw | 2.000s | 32.883us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 1.000s | 68.217us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dutycycle | 1 | 1 | 100.00 | |||
| pwm_rand_output | 31.000s | 21428.616us | 1 | 1 | 100.00 | |
| pulse | 1 | 1 | 100.00 | |||
| pwm_rand_output | 31.000s | 21428.616us | 1 | 1 | 100.00 | |
| blink | 1 | 1 | 100.00 | |||
| pwm_rand_output | 31.000s | 21428.616us | 1 | 1 | 100.00 | |
| heartbeat | 1 | 1 | 100.00 | |||
| pwm_rand_output | 31.000s | 21428.616us | 1 | 1 | 100.00 | |
| resolution | 1 | 1 | 100.00 | |||
| pwm_rand_output | 31.000s | 21428.616us | 1 | 1 | 100.00 | |
| multi_channel | 1 | 1 | 100.00 | |||
| pwm_rand_output | 31.000s | 21428.616us | 1 | 1 | 100.00 | |
| polarity | 1 | 1 | 100.00 | |||
| pwm_rand_output | 31.000s | 21428.616us | 1 | 1 | 100.00 | |
| phase | 2 | 2 | 100.00 | |||
| pwm_rand_output | 31.000s | 21428.616us | 1 | 1 | 100.00 | |
| pwm_phase | 22.000s | 11542.056us | 1 | 1 | 100.00 | |
| lowpower | 1 | 1 | 100.00 | |||
| pwm_rand_output | 31.000s | 21428.616us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| pwm_perf | 28.000s | 23333.906us | 1 | 1 | 100.00 | |
| regwen | 1 | 1 | 100.00 | |||
| pwm_regwen | 126.000s | 47745.364us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| pwm_stress_all | 103.000s | 51285.572us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| pwm_alert_test | 1.000s | 12.526us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| pwm_tl_errors | 2.000s | 393.901us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| pwm_tl_errors | 2.000s | 393.901us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| pwm_csr_hw_reset | 1.000s | 49.073us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 2.000s | 32.883us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 1.000s | 68.217us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 1.000s | 25.301us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| pwm_csr_hw_reset | 1.000s | 49.073us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 2.000s | 32.883us | 1 | 1 | 100.00 | |
| pwm_csr_aliasing | 1.000s | 68.217us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 1.000s | 25.301us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| pwm_tl_intg_err | 3.000s | 264.112us | 1 | 1 | 100.00 | |
| pwm_sec_cm | 1.000s | 39.574us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| pwm_tl_intg_err | 3.000s | 264.112us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| heartbeat_wrap | 1 | 1 | 100.00 | |||
| pwm_heartbeat_wrap | 27.000s | 15444.791us | 1 | 1 | 100.00 | |