Simulation Results: pwrmgr

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.76 %
  • code
  • 94.55 %
  • assert
  • 96.34 %
  • func
  • 96.38 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 94.20 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.610s 25.370us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.620s 23.989us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.600s 21.329us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.410s 117.965us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.740s 90.020us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.900s 76.263us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.600s 21.329us 1 1 100.00
pwrmgr_csr_aliasing 0.740s 90.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.740s 78.348us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.740s 78.348us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.900s 59.016us 1 1 100.00
pwrmgr_lowpower_invalid 0.720s 130.519us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.610s 58.527us 1 1 100.00
pwrmgr_reset_invalid 0.810s 101.102us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.610s 58.527us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.720s 140.696us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.760s 109.146us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.750s 95.422us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 3.410s 1307.717us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.710s 44.542us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.020s 60.626us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.020s 60.626us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 23.989us 1 1 100.00
pwrmgr_csr_rw 0.600s 21.329us 1 1 100.00
pwrmgr_csr_aliasing 0.740s 90.020us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 129.995us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 23.989us 1 1 100.00
pwrmgr_csr_rw 0.600s 21.329us 1 1 100.00
pwrmgr_csr_aliasing 0.740s 90.020us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 129.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.620s 10.525us 0 1 0.00
pwrmgr_sec_cm 0.670s 38.318us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.670s 38.318us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.670s 38.318us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.620s 10.525us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.470s 1510.759us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.720s 140.696us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.690s 62.737us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.630s 30.854us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.670s 38.318us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.670s 38.318us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.670s 38.318us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.590s 37.158us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.580s 57.704us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.730s 145.847us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 21.329us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 21.329us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.740s 146.427us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 8.470s 9955.567us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire 2 test runs
pwrmgr_tl_intg_err 102175234795479347670352322296643924867327488090797978372526810210302908471227 87
UVM_INFO @ 10525384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 13491152770733942423228509277735410976404283775108317786332570659814546041356 91
UVM_INFO @ 38317772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 68409316827091915085001172234851319247007211250636332068898105807504497662769 84
UVM_ERROR @ 146427274 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 146427274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---