Simulation Results: rom_ctrl/32kb

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.87 %
  • code
  • 99.59 %
  • assert
  • 96.66 %
  • func
  • 97.37 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.37 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.690s 175.003us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.270s 299.639us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.830s 372.432us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.390s 1072.422us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.880s 372.317us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.250s 193.592us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.830s 372.432us 1 1 100.00
rom_ctrl_csr_aliasing 2.880s 372.317us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.850s 435.238us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.840s 171.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.890s 1065.348us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.010s 476.915us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.170s 308.930us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.390s 533.797us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.510s 384.896us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.510s 384.896us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.270s 299.639us 1 1 100.00
rom_ctrl_csr_rw 2.830s 372.432us 1 1 100.00
rom_ctrl_csr_aliasing 2.880s 372.317us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.950s 166.766us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.270s 299.639us 1 1 100.00
rom_ctrl_csr_rw 2.830s 372.432us 1 1 100.00
rom_ctrl_csr_aliasing 2.880s 372.317us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.950s 166.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.770s 785.120us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 90.160s 1017.928us 1 1 100.00
rom_ctrl_tl_intg_err 20.860s 503.162us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 90.160s 1017.928us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 90.160s 1017.928us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 90.160s 1017.928us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 90.160s 1017.928us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.690s 175.003us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.690s 175.003us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.690s 175.003us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 20.860s 503.162us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
rom_ctrl_kmac_err_chk 7.170s 308.930us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.100s 1636.460us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.770s 785.120us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 90.160s 1017.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 77.710s 5956.332us 1 1 100.00