Simulation Results: rom_ctrl/64kb

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.23 %
  • code
  • 97.99 %
  • assert
  • 96.80 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.22 %
  • toggle
  • 99.69 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.490s 1628.970us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.410s 427.985us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.370s 543.725us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.430s 1268.688us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.170s 3120.896us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.020s 295.301us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.370s 543.725us 1 1 100.00
rom_ctrl_csr_aliasing 6.170s 3120.896us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.230s 956.480us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.020s 2781.062us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.290s 1467.731us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 36.390s 2100.180us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 11.550s 397.811us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.400s 544.304us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.890s 727.542us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.890s 727.542us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.410s 427.985us 1 1 100.00
rom_ctrl_csr_rw 6.370s 543.725us 1 1 100.00
rom_ctrl_csr_aliasing 6.170s 3120.896us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.700s 214.448us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.410s 427.985us 1 1 100.00
rom_ctrl_csr_rw 6.370s 543.725us 1 1 100.00
rom_ctrl_csr_aliasing 6.170s 3120.896us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.700s 214.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 49.640s 5969.483us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 220.230s 1059.312us 1 1 100.00
rom_ctrl_tl_intg_err 46.440s 1107.842us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 220.230s 1059.312us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 220.230s 1059.312us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 220.230s 1059.312us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 220.230s 1059.312us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.490s 1628.970us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.490s 1628.970us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.490s 1628.970us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 46.440s 1107.842us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
rom_ctrl_kmac_err_chk 11.550s 397.811us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 125.620s 9044.154us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 49.640s 5969.483us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 220.230s 1059.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 38.860s 1570.313us 1 1 100.00