Simulation Results: rstmgr

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 99.29 %
  • assert
  • 97.99 %
  • func
  • 95.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.33 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.240s 267.578us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.780s 111.526us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.780s 90.035us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.110s 804.279us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.290s 211.405us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.810s 117.065us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.780s 90.035us 1 1 100.00
rstmgr_csr_aliasing 1.290s 211.405us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.750s 183.112us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.560s 333.069us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.050s 166.534us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.280s 1695.287us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.280s 1695.287us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.280s 1695.287us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.280s 1695.287us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.390s 268.825us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.730s 77.402us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.930s 364.991us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.930s 364.991us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.780s 111.526us 1 1 100.00
rstmgr_csr_rw 0.780s 90.035us 1 1 100.00
rstmgr_csr_aliasing 1.290s 211.405us 1 1 100.00
rstmgr_same_csr_outstanding 1.330s 260.036us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.780s 111.526us 1 1 100.00
rstmgr_csr_rw 0.780s 90.035us 1 1 100.00
rstmgr_csr_aliasing 1.290s 211.405us 1 1 100.00
rstmgr_same_csr_outstanding 1.330s 260.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 19.670s 16799.035us 1 1 100.00
rstmgr_tl_intg_err 1.510s 478.609us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.670s 16799.035us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.670s 16799.035us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.510s 478.609us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.970s 184.284us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.310s 2267.891us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.940s 302.115us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.670s 16799.035us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 90.035us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 90.035us 1 1 100.00