Simulation Results: rv_timer

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.16 %
  • code
  • 99.79 %
  • assert
  • 96.82 %
  • func
  • 85.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 99.48 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.600s 114.285us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.520s 16.037us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.570s 94.452us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.870s 558.958us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.620s 42.705us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.840s 76.796us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.570s 94.452us 1 1 100.00
rv_timer_csr_aliasing 0.620s 42.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.860s 328.647us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.980s 2738.647us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.760s 225.359us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.760s 225.359us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.290s 3260.372us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.530s 26.722us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 19.763us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.270s 66.427us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.270s 66.427us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.520s 16.037us 1 1 100.00
rv_timer_csr_rw 0.570s 94.452us 1 1 100.00
rv_timer_csr_aliasing 0.620s 42.705us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 106.015us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.520s 16.037us 1 1 100.00
rv_timer_csr_rw 0.570s 94.452us 1 1 100.00
rv_timer_csr_aliasing 0.620s 42.705us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 106.015us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.820s 90.155us 1 1 100.00
rv_timer_tl_intg_err 0.940s 304.833us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.940s 304.833us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.610s 226.036us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.580s 148.601us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 4.610s 1466.217us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 80249928919531815751141155682789229200739410019234839448161721529653060619428 81
UVM_INFO @ 226036122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 1351478606504685876540552548954758163841076584297978892969312717214051376984 80
UVM_INFO @ 328647152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 82095225559882909112843299690713683316251526256280956931813948747508013192870 80
UVM_INFO @ 148601157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 71667744243784484271182221716025460972771839094143122330705579246605470887440 115
UVM_INFO @ 1466216941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---