Simulation Results: spi_device/1r1w

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.33 %
  • code
  • 93.18 %
  • assert
  • 94.39 %
  • func
  • 71.43 %
  • line
  • 98.87 %
  • branch
  • 98.18 %
  • cond
  • 95.97 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 51.430s 18571.105us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.800s 125.766us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.600s 67.358us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.470s 1257.822us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.940s 256.123us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.560s 29.729us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.600s 67.358us 1 1 100.00
spi_device_csr_aliasing 4.940s 256.123us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.630s 12.107us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.040s 64.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.670s 16.188us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.660s 4.134us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.650s 5.734us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.370s 461.207us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.370s 461.207us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 0.650s 25.408us 1 1 100.00
spi_device_tpm_sts_read 0.730s 23.481us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 19.560s 27246.974us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.290s 787.992us 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.360s 20519.231us 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.360s 20519.231us 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.480s 916.719us 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.480s 916.719us 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.480s 916.719us 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.480s 916.719us 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.480s 916.719us 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.080s 1046.709us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 26.420s 46310.438us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 26.420s 46310.438us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 26.420s 46310.438us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 9.690s 1325.388us 1 1 100.00
spi_device_read_buffer_direct 2.390s 886.119us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 26.420s 46310.438us 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 3.620s 489.134us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 14.000s 9879.856us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 14.000s 9879.856us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 51.430s 18571.105us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 190.220s 148232.035us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 211.220s 70661.151us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.650s 13.323us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.670s 26.677us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.420s 480.657us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.420s 480.657us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 125.766us 1 1 100.00
spi_device_csr_rw 1.600s 67.358us 1 1 100.00
spi_device_csr_aliasing 4.940s 256.123us 1 1 100.00
spi_device_same_csr_outstanding 1.480s 106.852us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 125.766us 1 1 100.00
spi_device_csr_rw 1.600s 67.358us 1 1 100.00
spi_device_csr_aliasing 4.940s 256.123us 1 1 100.00
spi_device_same_csr_outstanding 1.480s 106.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.920s 374.655us 1 1 100.00
spi_device_tl_intg_err 4.890s 224.536us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 4.890s 224.536us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 9.730s 1812.856us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 39281711822515669303678452651601928568676110386346477884523298835693776670786 81
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3414406 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3414406 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[947])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 68399572648410588771062202483764478149986735292238852496604179437257182573607 81
UVM_ERROR @ 3261874 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe0e562 [111000001110010101100010] vs 0x0 [0])
UVM_ERROR @ 3316874 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf3a8a [11110011101010001010] vs 0x0 [0])
UVM_ERROR @ 3346874 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x39e947 [1110011110100101000111] vs 0x0 [0])
UVM_ERROR @ 3421874 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x459b40 [10001011001101101000000] vs 0x0 [0])