Simulation Results: spi_device/2p

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.87 %
  • code
  • 94.05 %
  • assert
  • 94.62 %
  • func
  • 77.93 %
  • line
  • 98.91 %
  • branch
  • 98.28 %
  • cond
  • 95.95 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 10.820s 4722.017us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.820s 15.648us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.190s 131.876us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 25.510s 2758.352us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.700s 114.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.970s 86.786us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.190s 131.876us 1 1 100.00
spi_device_csr_aliasing 4.700s 114.091us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.640s 11.867us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.030s 56.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.710s 17.261us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.900s 90.330us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.740s 24.670us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.040s 661.603us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.040s 661.603us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.950s 1312.182us 1 1 100.00
spi_device_tpm_sts_read 0.820s 19.302us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 17.490s 16890.569us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.620s 100.622us 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.620s 15042.841us 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.620s 15042.841us 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.540s 40.762us 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.540s 40.762us 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.540s 40.762us 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.540s 40.762us 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.540s 40.762us 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.930s 1192.398us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 5.070s 504.023us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 5.070s 504.023us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 5.070s 504.023us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.940s 980.193us 1 1 100.00
spi_device_read_buffer_direct 5.040s 5051.469us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 5.070s 504.023us 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 25.830s 3654.284us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 16.490s 8219.599us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 16.490s 8219.599us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 10.820s 4722.017us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 175.340s 129553.812us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 186.560s 113104.160us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.670s 53.113us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.630s 77.113us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.790s 193.778us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.790s 193.778us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.820s 15.648us 1 1 100.00
spi_device_csr_rw 2.190s 131.876us 1 1 100.00
spi_device_csr_aliasing 4.700s 114.091us 1 1 100.00
spi_device_same_csr_outstanding 1.430s 145.392us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.820s 15.648us 1 1 100.00
spi_device_csr_rw 2.190s 131.876us 1 1 100.00
spi_device_csr_aliasing 4.700s 114.091us 1 1 100.00
spi_device_same_csr_outstanding 1.430s 145.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.970s 218.147us 1 1 100.00
spi_device_tl_intg_err 5.880s 2367.256us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.880s 2367.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 202.370s 299448.544us 1 1 100.00