Simulation Results: spi_host

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.12 %
  • code
  • 94.93 %
  • assert
  • 93.18 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 87.60 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 5.000s 1267.445us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 16.914us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 15.951us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 720.580us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 59.809us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 116.568us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 15.951us 1 1 100.00
spi_host_csr_aliasing 2.000s 59.809us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 30.636us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 31.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 21.398us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 61.835us 1 1 100.00
spi_host_error_cmd 1.000s 55.713us 1 1 100.00
spi_host_event 399.000s 30757.756us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 39.837us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 39.837us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 39.837us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 370.772us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 41.701us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 39.837us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 39.837us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 5.000s 1267.445us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 5.000s 1267.445us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 4.000s 587.499us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 1031.591us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 5.000s 900.507us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 1.000s 155.161us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 61.835us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 17.449us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 15.705us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 44.159us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 44.159us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 16.914us 1 1 100.00
spi_host_csr_rw 2.000s 15.951us 1 1 100.00
spi_host_csr_aliasing 2.000s 59.809us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 120.607us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 16.914us 1 1 100.00
spi_host_csr_rw 2.000s 15.951us 1 1 100.00
spi_host_csr_aliasing 2.000s 59.809us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 120.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 371.388us 1 1 100.00
spi_host_sec_cm 1.000s 144.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 371.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 25.000s 1801.975us 1 1 100.00