Simulation Results: sram_ctrl/main

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 96.77 %
  • assert
  • 96.46 %
  • func
  • 92.00 %
  • block
  • 96.01 %
  • line
  • 96.81 %
  • branch
  • 94.17 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 702.712us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 84.689us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 93.207us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 255.736us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.952us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 471.146us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 93.207us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.952us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 164.000s 5256.113us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 43.000s 3172.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 4.000s 977.821us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 68.000s 2671.697us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 118.000s 11873.189us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 69.000s 136818.516us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 45.000s 73124.552us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 20.000s 10274.853us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 2922.517us 1 1 100.00
sram_ctrl_partial_access_b2b 106.000s 17915.771us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 1357.010us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 1372.794us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 6032.048us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 3550.820us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1355.155us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 230.000s 128199.094us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 33.736us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 74.157us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 74.157us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 84.689us 1 1 100.00
sram_ctrl_csr_rw 1.000s 93.207us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.952us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 53.690us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 84.689us 1 1 100.00
sram_ctrl_csr_rw 1.000s 93.207us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.952us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 53.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 7082.333us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 453.371us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 373.397us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 453.371us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 373.397us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 3550.820us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 3550.820us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 93.207us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 20.000s 10274.853us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 10274.853us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 10274.853us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 45.000s 73124.552us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 683.184us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 7082.333us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 1363.672us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 702.712us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 702.712us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 20.000s 10274.853us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 453.371us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 45.000s 73124.552us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 453.371us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 453.371us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 702.712us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 453.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 23.000s 13883.463us 1 1 100.00