Simulation Results: sysrst_ctrl

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.28 %
  • code
  • 90.19 %
  • assert
  • 89.37 %
  • func
  • 61.27 %
  • line
  • 95.61 %
  • branch
  • 96.26 %
  • cond
  • 93.03 %
  • toggle
  • 100.00 %
  • FSM
  • 66.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.140s 2112.743us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.170s 2509.870us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.200s 2232.114us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.310s 2292.109us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.350s 6096.912us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.960s 2057.619us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 7.060s 3538.591us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.990s 2546.354us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.280s 2072.242us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.960s 2057.619us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.990s 2546.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 224.790s 124323.541us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 15.540s 35237.081us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.020s 3285.369us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.910s 3543.984us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.870s 2522.356us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.700s 2196.792us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.270s 3687.648us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.870s 2613.112us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.170s 4715.990us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 54.150s 30429.790us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 6.800s 6346.079us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.840s 2022.242us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.510s 2024.808us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.190s 2281.757us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.190s 2281.757us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.350s 6096.912us 1 1 100.00
sysrst_ctrl_csr_rw 3.960s 2057.619us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.990s 2546.354us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.520s 4867.841us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.350s 6096.912us 1 1 100.00
sysrst_ctrl_csr_rw 3.960s 2057.619us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.990s 2546.354us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.520s 4867.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 10.840s 22076.454us 1 1 100.00
sysrst_ctrl_tl_intg_err 74.940s 42396.708us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 74.940s 42396.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 13.080s 6218.715us 1 1 100.00