Simulation Results: uart

 
13/05/2026 15:30:31 DVSim: v1.34.0 sha: cadc156 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.20 %
  • code
  • 96.14 %
  • assert
  • 97.12 %
  • func
  • 56.34 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 96.62 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.590s 680.023us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.590s 13.422us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 28.610us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.160s 96.418us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.680s 78.491us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.700s 73.924us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 28.610us 1 1 100.00
uart_csr_aliasing 0.680s 78.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 56.400s 41198.097us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.590s 680.023us 1 1 100.00
uart_tx_rx 56.400s 41198.097us 1 1 100.00
parity_error 2 2 100.00
uart_intr 6.530s 7367.104us 1 1 100.00
uart_rx_parity_err 126.780s 117167.776us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 56.400s 41198.097us 1 1 100.00
uart_intr 6.530s 7367.104us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 38.950s 43836.872us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 11.040s 55438.110us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 43.510s 41957.498us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 6.530s 7367.104us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 6.530s 7367.104us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 6.530s 7367.104us 1 1 100.00
perf 1 1 100.00
uart_perf 99.110s 6007.029us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.210s 10230.437us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.210s 10230.437us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 0.920s 308.929us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.870s 3158.418us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.100s 733.119us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 32.880s 6055.317us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 333.300s 151443.299us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 276.480s 234998.098us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.560s 13.700us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.590s 41.935us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.690s 466.471us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.690s 466.471us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.590s 13.422us 1 1 100.00
uart_csr_rw 0.610s 28.610us 1 1 100.00
uart_csr_aliasing 0.680s 78.491us 1 1 100.00
uart_same_csr_outstanding 0.690s 87.967us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.590s 13.422us 1 1 100.00
uart_csr_rw 0.610s 28.610us 1 1 100.00
uart_csr_aliasing 0.680s 78.491us 1 1 100.00
uart_same_csr_outstanding 0.690s 87.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.760s 68.261us 1 1 100.00
uart_tl_intg_err 0.820s 42.049us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.820s 42.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 32.930s 4905.319us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 103522504172483844304638141569903409576690807716714397952472768728259715979954 79
UVM_ERROR @ 116679245 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 116689883 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 116700521 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 116711159 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 111 [0x6f]) reg name: uart_reg_block.rdata