Simulation Results: adc_ctrl

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.73 %
  • code
  • 92.30 %
  • assert
  • 91.90 %
  • func
  • 12.99 %
  • line
  • 98.13 %
  • branch
  • 96.41 %
  • cond
  • 86.10 %
  • toggle
  • 99.76 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.160s 5952.016us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.780s 1073.000us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.260s 473.749us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 6.870s 13035.884us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.320s 907.402us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.460s 613.173us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.260s 473.749us 1 1 100.00
adc_ctrl_csr_aliasing 1.320s 907.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.150s 307.703us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.360s 524.074us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 2.060s 468.593us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.000s 294.211us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.210s 305.346us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 1.000s 356.294us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.540s 316.218us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 2.180s 458.135us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.470s 3283.866us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 7.590s 43757.128us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 181.340s 107652.602us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.870s 765.640us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.010s 321.389us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.840s 433.431us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.160s 583.804us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.160s 583.804us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.780s 1073.000us 1 1 100.00
adc_ctrl_csr_rw 1.260s 473.749us 1 1 100.00
adc_ctrl_csr_aliasing 1.320s 907.402us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.860s 4212.434us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.780s 1073.000us 1 1 100.00
adc_ctrl_csr_rw 1.260s 473.749us 1 1 100.00
adc_ctrl_csr_aliasing 1.320s 907.402us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.860s 4212.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 7.730s 8027.773us 1 1 100.00
adc_ctrl_tl_intg_err 6.270s 8397.492us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.270s 8397.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 3.700s 1942.008us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 100077217678067042596700904816449532992332020666493052236817244821000830429168 388
UVM_INFO @ 307703458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 27168589348382007073735082972377830107118483308913123949566992584253996752672 388
UVM_INFO @ 524073820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 61581042279651366958859927861925943611883311394361226540350996307422509863687 388
UVM_INFO @ 468592910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 37309902345195007011740086632864402002439438819590734681634902819316870740065 388
UVM_INFO @ 294210854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 43081777355848611425839204151731837511204890529616939648112504609301629766331 388
UVM_INFO @ 305345773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 47228136581149275137589783553765978463598026332025034414767532353261429674408 388
UVM_INFO @ 356293792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 56390172789015345284618437512162236099227988925160579604077488711259965661794 388
UVM_INFO @ 458135146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 61879700170643950226192886290670036596664586855302093674802847773077781013947 388
UVM_INFO @ 316217821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 64600348521003475029545237576348320612468381669493354445801193918140431433123 414
UVM_INFO @ 1942008369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 107800574921546461156683815114008220502277448283162880215713532235262635659036 389
UVM_INFO @ 765640276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---