Simulation Results: aes/masked

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.15 %
  • code
  • 93.58 %
  • assert
  • 98.23 %
  • func
  • 75.63 %
  • block
  • 94.20 %
  • line
  • 95.86 %
  • branch
  • 87.14 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 126.849us 1 1 100.00
smoke 1 1 100.00
aes_smoke 5.000s 222.656us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 66.324us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 64.688us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 1426.509us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 1307.925us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 141.918us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 64.688us 1 1 100.00
aes_csr_aliasing 3.000s 1307.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 5.000s 222.656us 1 1 100.00
aes_config_error 2.000s 130.657us 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
key_length 3 3 100.00
aes_smoke 5.000s 222.656us 1 1 100.00
aes_config_error 2.000s 130.657us 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 93.589us 1 1 100.00
aes_b2b 9.000s 535.833us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 5.000s 222.656us 1 1 100.00
aes_config_error 2.000s 130.657us 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
aes_alert_reset 3.000s 269.489us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 89.064us 1 1 100.00
aes_config_error 2.000s 130.657us 1 1 100.00
aes_alert_reset 3.000s 269.489us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 76.011us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 606.471us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 269.489us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 93.589us 1 1 100.00
aes_sideload 4.000s 134.862us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 188.418us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 174.000s 41124.014us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 62.290us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 281.524us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 281.524us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 66.324us 1 1 100.00
aes_csr_rw 2.000s 64.688us 1 1 100.00
aes_csr_aliasing 3.000s 1307.925us 1 1 100.00
aes_same_csr_outstanding 2.000s 59.002us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 66.324us 1 1 100.00
aes_csr_rw 2.000s 64.688us 1 1 100.00
aes_csr_aliasing 3.000s 1307.925us 1 1 100.00
aes_same_csr_outstanding 2.000s 59.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 175.375us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 82.880us 1 1 100.00
aes_control_fi 2.000s 62.583us 1 1 100.00
aes_cipher_fi 26.000s 10007.883us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 329.777us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 329.777us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 329.777us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 329.777us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 95.967us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 235.083us 1 1 100.00
aes_tl_intg_err 2.000s 389.415us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 389.415us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 269.489us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 329.777us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 329.777us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 5.000s 222.656us 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
aes_alert_reset 3.000s 269.489us 1 1 100.00
aes_core_fi 2.000s 114.092us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 130.657us 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
aes_core_fi 2.000s 114.092us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 329.777us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 68.927us 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 93.589us 1 1 100.00
aes_sideload 4.000s 134.862us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 68.927us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 68.927us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 68.927us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 68.927us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 68.927us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 93.589us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 82.880us 1 1 100.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 82.880us 1 1 100.00
aes_control_fi 2.000s 62.583us 1 1 100.00
aes_cipher_fi 26.000s 10007.883us 0 1 0.00
aes_ctr_fi 3.000s 149.022us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 82.880us 1 1 100.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 82.880us 1 1 100.00
aes_control_fi 2.000s 62.583us 1 1 100.00
aes_cipher_fi 26.000s 10007.883us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 26.000s 10007.883us 0 1 0.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 82.880us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 4.000s 82.880us 1 1 100.00
aes_control_fi 2.000s 62.583us 1 1 100.00
aes_ctr_fi 3.000s 149.022us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 4.000s 82.880us 1 1 100.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 82.880us 1 1 100.00
aes_control_fi 2.000s 62.583us 1 1 100.00
aes_cipher_fi 26.000s 10007.883us 0 1 0.00
aes_ctr_fi 3.000s 149.022us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 269.489us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 82.880us 1 1 100.00
aes_control_fi 2.000s 62.583us 1 1 100.00
aes_cipher_fi 26.000s 10007.883us 0 1 0.00
aes_ctr_fi 3.000s 149.022us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 82.880us 1 1 100.00
aes_control_fi 2.000s 62.583us 1 1 100.00
aes_cipher_fi 26.000s 10007.883us 0 1 0.00
aes_ctr_fi 3.000s 149.022us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 4.000s 82.880us 1 1 100.00
aes_control_fi 2.000s 62.583us 1 1 100.00
aes_ctr_fi 3.000s 149.022us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 1 100.00
aes_fi 4.000s 82.880us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 82.880us 1 1 100.00
aes_control_fi 2.000s 62.583us 1 1 100.00
aes_cipher_fi 26.000s 10007.883us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 11.000s 448.253us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 38553232639621718562185015249614070824216902633296658240347424880817090682396 145
UVM_INFO @ 10007883322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 100042410639926317340827687090432985909235066437136044816176766748025047239804 202
UVM_INFO @ 448253416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---