Simulation Results: alert_handler

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.07 %
  • code
  • 88.67 %
  • assert
  • 97.49 %
  • func
  • 78.04 %
  • line
  • 99.55 %
  • branch
  • 98.35 %
  • cond
  • 91.42 %
  • toggle
  • 86.27 %
  • FSM
  • 67.74 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 9.900s 525.807us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.330s 413.698us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 6.050s 118.625us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 59.800s 3270.095us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 79.420s 2511.348us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.010s 44.220us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 6.050s 118.625us 1 1 100.00
alert_handler_csr_aliasing 79.420s 2511.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 25.890s 1612.631us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 45.120s 4937.706us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1550.970s 43253.740us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 17.240s 924.558us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 9.900s 525.807us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 22.150s 810.078us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 15.680s 361.205us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 12.000s 3507.398us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1237.530s 79164.107us 1 1 100.00
alert_handler_lpg_stub_clk 1081.290s 94667.570us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 342.200s 21880.237us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 7.970s 171.346us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.560s 177.674us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.990s 17.138us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 8.910s 219.741us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 8.910s 219.741us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.330s 413.698us 1 1 100.00
alert_handler_csr_rw 6.050s 118.625us 1 1 100.00
alert_handler_csr_aliasing 79.420s 2511.348us 1 1 100.00
alert_handler_same_csr_outstanding 12.760s 168.963us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.330s 413.698us 1 1 100.00
alert_handler_csr_rw 6.050s 118.625us 1 1 100.00
alert_handler_csr_aliasing 79.420s 2511.348us 1 1 100.00
alert_handler_same_csr_outstanding 12.760s 168.963us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 117.140s 3244.208us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 117.140s 3244.208us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 117.140s 3244.208us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 117.140s 3244.208us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 699.470s 28440.244us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
alert_handler_tl_intg_err 26.660s 2813.879us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 26.660s 2813.879us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 117.140s 3244.208us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 9.900s 525.807us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 9.900s 525.807us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 9.900s 525.807us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 9.900s 525.807us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 17.240s 924.558us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1237.530s 79164.107us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 17.240s 924.558us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1550.970s 43253.740us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1550.970s 43253.740us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 72.930s 2979.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 15.830s 1631.923us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. 1 test run
alert_handler_ping_timeout 38479309285622157962334174791606965243003041027252099459890060433628570063693 80
UVM_INFO @ 3507398356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 87520678276235896738397228619752798588261262074437626944202237231561012518624 198
UVM_INFO @ 171346164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 52483938246570646046343565167939922290345291934573397343668543851717293187305 88
UVM_INFO @ 1631923492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---