Simulation Results: chip

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.05 %
  • code
  • 85.25 %
  • assert
  • 97.37 %
  • func
  • 42.54 %
  • line
  • 94.44 %
  • branch
  • 94.04 %
  • cond
  • 89.42 %
  • toggle
  • 91.20 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.34%
V2S
100.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 135.460s 2477.018us 1 1 100.00
chip_sw_example_rom 85.400s 2317.961us 1 1 100.00
chip_sw_example_manufacturer 124.060s 2137.385us 1 1 100.00
chip_sw_example_concurrency 186.620s 3132.263us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 306.030s 7223.643us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 382.490s 5629.890us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 237.430s 4583.435us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5109.840s 33589.217us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 60.320s 2064.542us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5109.840s 33589.217us 1 1 100.00
chip_csr_rw 382.490s 5629.890us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.070s 196.452us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 306.510s 4240.664us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 306.510s 4240.664us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 306.510s 4240.664us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 413.110s 4348.133us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 413.110s 4348.133us 1 1 100.00
chip_sw_uart_tx_rx_idx1 321.370s 5054.793us 1 1 100.00
chip_sw_uart_tx_rx_idx2 415.950s 4635.235us 1 1 100.00
chip_sw_uart_tx_rx_idx3 402.620s 4347.654us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 311.490s 3675.096us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1053.550s 8790.246us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 299.290s 4589.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 254.640s 5677.176us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 254.640s 5677.176us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 157.090s 3163.472us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 209.010s 3578.825us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 173.000s 2931.908us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 129.550s 3128.016us 1 1 100.00
chip_tap_straps_testunlock0 97.410s 2279.503us 1 1 100.00
chip_tap_straps_rma 301.570s 5620.926us 1 1 100.00
chip_tap_straps_prod 1127.100s 16093.566us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 148.830s 3224.457us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 912.620s 9963.108us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 518.780s 5913.135us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 518.780s 5913.135us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 641.700s 7621.170us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 724.580s 9682.573us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 336.760s 4310.699us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 609.170s 6131.063us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3874.280s 18886.953us 1 1 100.00
chip_sw_aes_enc_jitter_en 176.230s 2805.628us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 599.190s 6635.533us 1 1 100.00
chip_sw_hmac_enc_jitter_en 196.650s 3593.744us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1171.890s 9535.286us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 241.030s 3915.890us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 355.980s 4983.081us 1 1 100.00
chip_sw_clkmgr_jitter 156.750s 3235.837us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 169.940s 2364.705us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 790.200s 9725.471us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 279.720s 5389.313us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 133.390s 2494.843us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 279.720s 5389.313us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 153.500s 2951.803us 1 1 100.00
chip_sw_aes_smoketest 214.800s 3233.502us 1 1 100.00
chip_sw_aon_timer_smoketest 191.330s 3141.993us 1 1 100.00
chip_sw_clkmgr_smoketest 173.770s 3424.511us 1 1 100.00
chip_sw_csrng_smoketest 217.410s 3406.884us 1 1 100.00
chip_sw_entropy_src_smoketest 953.300s 7288.579us 1 1 100.00
chip_sw_gpio_smoketest 187.730s 2928.354us 1 1 100.00
chip_sw_hmac_smoketest 249.920s 3448.731us 1 1 100.00
chip_sw_kmac_smoketest 178.410s 3378.565us 1 1 100.00
chip_sw_otbn_smoketest 1557.680s 10427.308us 1 1 100.00
chip_sw_pwrmgr_smoketest 290.480s 5897.933us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 267.260s 6703.232us 1 1 100.00
chip_sw_rv_plic_smoketest 168.430s 2882.103us 1 1 100.00
chip_sw_rv_timer_smoketest 200.400s 3346.409us 1 1 100.00
chip_sw_rstmgr_smoketest 190.210s 3162.948us 1 1 100.00
chip_sw_sram_ctrl_smoketest 159.130s 2756.880us 1 1 100.00
chip_sw_uart_smoketest 173.520s 3194.928us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 171.210s 3374.785us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 314.370s 4405.184us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8655.120s 63390.816us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3285.700s 16045.641us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 127.271s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 177.170s 2894.120us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 221.330s 3717.128us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7283.500s 54376.015us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7664.050s 57498.968us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 69.840s 2635.685us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 69.840s 2635.685us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5109.840s 33589.217us 1 1 100.00
chip_same_csr_outstanding 1608.440s 15862.914us 1 1 100.00
chip_csr_hw_reset 306.030s 7223.643us 1 1 100.00
chip_csr_rw 382.490s 5629.890us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5109.840s 33589.217us 1 1 100.00
chip_same_csr_outstanding 1608.440s 15862.914us 1 1 100.00
chip_csr_hw_reset 306.030s 7223.643us 1 1 100.00
chip_csr_rw 382.490s 5629.890us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 30.730s 1244.528us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.300s 46.384us 1 1 100.00
xbar_smoke_large_delays 43.980s 6915.969us 1 1 100.00
xbar_smoke_slow_rsp 50.280s 5892.389us 1 1 100.00
xbar_random_zero_delays 26.980s 528.265us 1 1 100.00
xbar_random_large_delays 64.580s 10704.662us 1 1 100.00
xbar_random_slow_rsp 94.680s 10899.615us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 12.880s 302.380us 1 1 100.00
xbar_error_and_unmapped_addr 5.060s 83.616us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 36.710s 1700.270us 1 1 100.00
xbar_error_and_unmapped_addr 5.060s 83.616us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 34.870s 823.050us 1 1 100.00
xbar_access_same_device_slow_rsp 594.440s 67770.774us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 13.940s 271.648us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 152.350s 5490.616us 1 1 100.00
xbar_stress_all_with_error 305.160s 12216.123us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 110.920s 1140.427us 1 1 100.00
xbar_stress_all_with_reset_error 119.340s 1128.340us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3285.700s 16045.641us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2573.210s 25161.762us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3173.340s 15328.224us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 79.446s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 70.870s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 96.320s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 61.659s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 54.092s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 184.558s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 101.245s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 64.575s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 62.989s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 67.093s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 178.746s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 103.842s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 84.759s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 18.157s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 88.495s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 18.370s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 21.780s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 20.740s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 20.390s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 22.180s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.210s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 19.830s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 20.810s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 22.250s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 20.290s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.960s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.590s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 19.960s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 22.090s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.440s 10.320us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 170.194s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 41.445s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 130.926s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 31.909s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 25.285s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 6188.530s 29986.331us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 6199.480s 29403.381us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3124.740s 15255.776us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3090.710s 15936.551us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3412.750s 34831.431us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3412.750s 34831.431us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 218.880s 3450.501us 1 1 100.00
chip_sw_aes_enc_jitter_en 176.230s 2805.628us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 188.720s 3252.097us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 181.050s 2876.465us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1649.560s 13072.228us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 217.110s 2749.970us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 359.890s 5417.692us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 477.870s 6027.883us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 574.710s 5748.907us 1 1 100.00
chip_plic_all_irqs_10 276.470s 3589.108us 1 1 100.00
chip_plic_all_irqs_20 386.450s 3724.819us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 208.770s 3093.871us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 954.740s 9476.718us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 186.510s 3034.935us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 128.440s 2911.126us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.168s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 778.040s 6769.249us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1071.430s 7574.152us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 827.670s 7985.006us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8277.590s 255393.558us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 238.220s 3648.845us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 290.480s 5897.933us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 238.220s 3648.845us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 413.640s 7625.990us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 413.640s 7625.990us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 410.200s 7417.682us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 335.210s 4746.925us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 667.840s 6343.342us 1 1 100.00
chip_sw_aes_idle 181.050s 2876.465us 1 1 100.00
chip_sw_hmac_enc_idle 170.740s 3065.544us 1 1 100.00
chip_sw_kmac_idle 184.420s 2601.708us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 353.890s 4696.442us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 277.310s 4858.445us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 305.860s 4470.099us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 334.200s 4566.245us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 832.140s 11699.693us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 447.070s 4241.692us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 383.030s 5289.034us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 442.590s 4815.126us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 392.870s 4540.879us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 409.140s 3822.353us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 375.740s 4617.663us 1 1 100.00
chip_sw_ast_clk_outputs 641.700s 7621.170us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 541.890s 10177.178us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 442.590s 4815.126us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 392.870s 4540.879us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 336.760s 4310.699us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 609.170s 6131.063us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3874.280s 18886.953us 1 1 100.00
chip_sw_aes_enc_jitter_en 176.230s 2805.628us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 599.190s 6635.533us 1 1 100.00
chip_sw_hmac_enc_jitter_en 196.650s 3593.744us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1171.890s 9535.286us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 241.030s 3915.890us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 355.980s 4983.081us 1 1 100.00
chip_sw_clkmgr_jitter 156.750s 3235.837us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 174.770s 3232.708us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 414.120s 4812.778us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 714.350s 6652.996us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4213.550s 25372.532us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 171.050s 3918.564us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 181.470s 3809.670us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 962.820s 10551.845us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 226.640s 3684.645us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 396.730s 4972.832us 1 1 100.00
chip_sw_flash_init_reduced_freq 1229.230s 17639.237us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 13599.460s 149297.059us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 641.700s 7621.170us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 383.210s 4606.639us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 249.190s 3401.690us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 477.870s 6027.883us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 778.040s 6769.249us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2082.390s 24660.291us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 177.300s 3150.017us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 460.580s 5861.447us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 145.210s 3219.192us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 4652.840s 24616.235us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 221.280s 3323.727us 1 1 100.00
chip_sw_edn_entropy_reqs 621.470s 5711.574us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 221.280s 3323.727us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2082.390s 24660.291us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 152.710s 2944.486us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1208.330s 21244.223us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 600.530s 5038.396us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 609.170s 6131.063us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 379.640s 4200.507us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 336.760s 4310.699us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3865.770s 42634.251us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1208.330s 21244.223us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 240.820s 3731.281us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1503.580s 11468.027us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 151.760s 2787.363us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3865.770s 42634.251us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 151.760s 2787.363us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 151.760s 2787.363us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 151.760s 2787.363us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 151.760s 2787.363us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 477.870s 6027.883us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 125.740s 4986.815us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 557.330s 5332.145us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 385.040s 5727.513us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 385.040s 5727.513us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 152.470s 3032.381us 1 1 100.00
chip_sw_hmac_enc_jitter_en 196.650s 3593.744us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 170.740s 3065.544us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 971.820s 7138.042us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 683.410s 5661.021us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 442.060s 5497.232us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 445.350s 5352.025us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 435.930s 4606.247us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 292.830s 3836.086us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1503.580s 11468.027us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1171.890s 9535.286us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 779.260s 6670.419us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1649.560s 13072.228us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2740.750s 15707.068us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 192.400s 2867.624us 1 1 100.00
chip_sw_kmac_mode_kmac 181.550s 3181.557us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 241.030s 3915.890us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1503.580s 11468.027us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 760.290s 14029.390us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 144.580s 3387.155us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1161.870s 8418.638us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 184.420s 2601.708us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 359.890s 5417.692us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 129.550s 3128.016us 1 1 100.00
chip_tap_straps_rma 301.570s 5620.926us 1 1 100.00
chip_tap_straps_prod 1127.100s 16093.566us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 151.120s 2723.665us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 760.290s 14029.390us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 760.290s 14029.390us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 760.290s 14029.390us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 933.500s 8392.534us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 151.760s 2787.363us 0 1 0.00
chip_sw_flash_rma_unlocked 3865.770s 42634.251us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 215.250s 2790.576us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 602.280s 7729.991us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 695.710s 7987.921us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 483.320s 6196.833us 0 1 0.00
chip_sw_lc_ctrl_transition 760.290s 14029.390us 1 1 100.00
chip_sw_keymgr_key_derivation 1503.580s 11468.027us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 393.080s 8283.152us 1 1 100.00
chip_sw_sram_ctrl_execution_main 751.160s 10856.198us 1 1 100.00
chip_prim_tl_access 125.740s 4986.815us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 541.890s 10177.178us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 447.070s 4241.692us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 383.030s 5289.034us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 442.590s 4815.126us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 392.870s 4540.879us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 409.140s 3822.353us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 375.740s 4617.663us 1 1 100.00
chip_tap_straps_dev 129.550s 3128.016us 1 1 100.00
chip_tap_straps_rma 301.570s 5620.926us 1 1 100.00
chip_tap_straps_prod 1127.100s 16093.566us 1 1 100.00
chip_rv_dm_lc_disabled 557.000s 13600.807us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 136.280s 3045.873us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 96.750s 3103.455us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 82.560s 3005.361us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 196.070s 3299.854us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1739.960s 24733.211us 1 1 100.00
chip_rv_dm_lc_disabled 557.000s 13600.807us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 581.290s 7859.784us 0 1 0.00
chip_sw_lc_walkthrough_prod 621.050s 10353.809us 0 1 0.00
chip_sw_lc_walkthrough_prodend 732.760s 9036.434us 1 1 100.00
chip_sw_lc_walkthrough_rma 376.720s 7028.649us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1739.960s 24733.211us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 61.430s 2496.871us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 57.390s 1912.225us 1 1 100.00
rom_volatile_raw_unlock 156.065s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3771.330s 17792.376us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3874.280s 18886.953us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 667.840s 6343.342us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 667.840s 6343.342us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 667.840s 6343.342us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 285.700s 3851.254us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 760.290s 14029.390us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1208.330s 21244.223us 1 1 100.00
chip_sw_otbn_mem_scramble 285.700s 3851.254us 1 1 100.00
chip_sw_keymgr_key_derivation 1503.580s 11468.027us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 407.020s 4554.143us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 160.770s 2763.175us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1208.330s 21244.223us 1 1 100.00
chip_sw_otbn_mem_scramble 285.700s 3851.254us 1 1 100.00
chip_sw_keymgr_key_derivation 1503.580s 11468.027us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 407.020s 4554.143us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 160.770s 2763.175us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 760.290s 14029.390us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 366.480s 5116.726us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 151.120s 2723.665us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 215.250s 2790.576us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 602.280s 7729.991us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 695.710s 7987.921us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 483.320s 6196.833us 0 1 0.00
chip_sw_lc_ctrl_transition 760.290s 14029.390us 1 1 100.00
chip_prim_tl_access 125.740s 4986.815us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 125.740s 4986.815us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 889.150s 8216.267us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 181.950s 6233.298us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 968.510s 22789.943us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 309.600s 7763.416us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 284.950s 7439.615us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 494.320s 6862.846us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1082.980s 25851.919us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 509.860s 10825.890us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 413.640s 7625.990us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 979.050s 14268.059us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 391.230s 6063.393us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 181.950s 6233.298us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 360.290s 5436.857us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1096.690s 22637.794us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 291.720s 5776.927us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 145.860s 2593.064us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 268.280s 5498.630us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 631.030s 8102.268us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 973.910s 10964.798us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2214.190s 27125.753us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 165.210s 3306.092us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 477.870s 6027.883us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 393.080s 8283.152us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 393.080s 8283.152us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 973.910s 10964.798us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 268.280s 5498.630us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 391.230s 6063.393us 1 1 100.00
chip_sw_pwrmgr_smoketest 290.480s 5897.933us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 279.310s 3904.404us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 508.970s 7139.254us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 209.820s 4214.224us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 954.740s 9476.718us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 170.470s 2782.243us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 477.870s 6027.883us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1071.430s 7574.152us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 446.460s 4800.384us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 520.760s 5468.530us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 195.080s 3127.401us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 160.770s 2763.175us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 508.970s 7139.254us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 508.970s 7139.254us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1248.090s 17156.747us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 991.420s 13560.640us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 279.310s 3904.404us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 183.950s 2784.808us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 258.730s 6169.758us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 301.570s 5620.926us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 557.000s 13600.807us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 574.710s 5748.907us 1 1 100.00
chip_plic_all_irqs_10 276.470s 3589.108us 1 1 100.00
chip_plic_all_irqs_20 386.450s 3724.819us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 156.390s 2570.799us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 191.570s 3372.335us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3285.700s 16045.641us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 418.940s 6594.079us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 194.910s 2670.923us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 197.050s 3748.713us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 215.430s 3679.440us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 407.020s 4554.143us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 355.980s 4983.081us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 442.050s 8620.811us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 404.860s 7806.952us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 751.160s 10856.198us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 477.870s 6027.883us 1 1 100.00
chip_sw_data_integrity_escalation 518.780s 5913.135us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 631.030s 8102.268us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1033.650s 23035.779us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 201.050s 3362.583us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 276.560s 3880.632us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 381.940s 5161.515us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1033.650s 23035.779us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1033.650s 23035.779us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2560.150s 20441.309us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2560.150s 20441.309us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 343.330s 6749.494us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3412.750s 34831.431us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 171.110s 3180.561us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 173.870s 2509.543us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 315.990s 3907.253us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 349.940s 3514.172us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 993.840s 7626.999us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5418.990s 31335.683us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1878.340s 12648.598us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 129.340s 2700.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 205.390s 2971.808us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 103.410s 2255.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10487.820s 71727.335us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1162.480s 6380.675us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 185.370s 3989.554us 0 1 0.00
rom_e2e_jtag_debug_dev 160.560s 4556.124us 0 1 0.00
rom_e2e_jtag_debug_rma 198.310s 3427.421us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 74.970s 3469.064us 0 1 0.00
rom_e2e_jtag_inject_dev 83.800s 3084.742us 0 1 0.00
rom_e2e_jtag_inject_rma 71.240s 2471.315us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 65.421s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 257.330s 3353.355us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 325.850s 2631.848us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 488.340s 4122.155us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 771.950s 6556.106us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 227.740s 2303.693us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 628.790s 4935.143us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 135.010s 2832.607us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 196.700s 3268.775us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 305.840s 6843.342us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 343.570s 5905.812us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 973.910s 10964.798us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 185.370s 3989.554us 0 1 0.00
rom_e2e_jtag_debug_dev 160.560s 4556.124us 0 1 0.00
rom_e2e_jtag_debug_rma 198.310s 3427.421us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 369.280s 5041.579us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 477.870s 6027.883us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5673.400s 38001.346us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5673.400s 38001.346us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 162.020s 3171.593us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 413.110s 4348.133us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3261.140s 19034.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 207.420s 2948.434us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 20.050s 10.200us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 4.990s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 122.750s 2539.319us 1 1 100.00
chip_sw_otp_ctrl_descrambling 169.830s 3213.611us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 243.170s 4201.789us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.132s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 177.310s 3026.053us 1 1 100.00
ate_bootstrap_flash_erase 576.190s 10010.180us 0 1 0.00
ate_bootstrap_one_frame 6790.760s 44961.112us 1 1 100.00
ate_bootstrap_disjoint 9849.990s 84887.424us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 8239855675035413301066700612517366336225000254421050524043906079409428243924 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 88747495555869536045830280073251257861875378879000037841824604570034769691438 None
Another command (pid=369634) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=448863) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=370511) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 58183218241456397736962513861712254333186357948213423042559353183509784418520 None
Another command (pid=468900) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=383795) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=466292) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 77097905482255893290701443512718978152703350840631217285026765750789943334315 None
Another command (pid=602660) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=615669) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=592362) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 32883666169899514629060442530278355802772416320970905683558036380591488521902 None
Another command (pid=483619) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=409842) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=557845) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 115644280324206538705326727693032078151922874416210173778080618460844517249876 None
Another command (pid=652663) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=589048) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=560242) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 96076343368493923644137274636554174650348808677182719388900935863231339802486 None
Another command (pid=631175) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=631960) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=617891) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 111401984854998067980180956795415233415757141734431575321565916900796364690346 None
Another command (pid=592362) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=573416) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=578992) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 2060969745967487857350893058124164625542504742755427650911270903652342349170 None
Another command (pid=466619) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=462551) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=409842) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 78383367705595409130316002343713698624314392464897261426033108466410612058934 None
---- STDERR ----
Another command (pid=466619) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=462551) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 38099597282546225872527776362645738139846300320354188679978790687967762342933 None
Another command (pid=462551) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=409842) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=557845) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 100800450372983363508207314456670587039841349125856725087224862320533234507912 None
Another command (pid=615669) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=592362) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=573416) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 32872662857320968856529816773415496819780729500017948567918251686036719170927 None
Another command (pid=584490) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=568810) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=373329) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 97778287506892808445558462017863787188264031788239039687243905052888550890354 None
Another command (pid=417379) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=466619) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=462551) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 44788348100798946209121978918814436183100417710357218883787424900050251002346 None
---- STDERR ----
Another command (pid=418446) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 21513798757881317022593954792661367534205255064245810845580377358250098019039 None
Another command (pid=579531) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=582277) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=401807) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 60858394229091905375173410501052927164371747289859548037521758081350867615582 None
Another command (pid=468105) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=590765) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=567487) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 70308568641442406573010970911305925682979437332205316838890855639462785514520 None
Another command (pid=418446) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=438468) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=392919) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 14218035594200391600520569492699320133194127918061738463410096312879791941369 None
Another command (pid=593628) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=589465) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=591129) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 95815550619886828862366491014287025191174691125013974527107780969426744877488 None
Another command (pid=360839) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=442658) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=416187) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 114384433819118726177413932767551741120594099165355081855889639862635255054528 None
Another command (pid=442658) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=416187) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=418446) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 101597653656318493539012337269640639180008348017813491540342375303494301991688 None
Another command (pid=573416) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=578992) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=478571) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 75692040325493626621968432333795930205838069114195453266846082570456668192726 None
Another command (pid=409842) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=481498) is running. Waiting for it to complete on the server (server_pid=253297)...
Another command (pid=557845) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 83759802434022851323089096995347722635413137796125619355242389025411541227651 None
---- STDERR ----
Another command (pid=360839) is running. Waiting for it to complete on the server (server_pid=253297)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 81584143465646512001025348927125755218119778357793091386636448081592891944397 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 102088376491120640009927803189811810920027151666949699014579855503973120141310 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 64405553305213665267261447623647615619593993056415254738619103732613635598206 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 97447149539492377134544351655452273750033066983720404228729254857393421367890 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 27545371966774829892162709677373432503569388959618273387595227270583753423992 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 69423317511372374442793832381173154902480904376451044119859071690983026354502 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 30192771184514132792610647081329876273321529917618863454249883536824433010029 368
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 93419679336843794240450527189897820994592016097016333872280151588501749400516 368
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 28694387580440210787266632405665754536595543108120989346214802801873729936273 368
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 66183098667378637669023051112610030495880378763123390288196159402583751462108 328
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 48344792502071689128587912618931695418295334229183232134284678960939888185033 328
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 66059706240555281907757415213691935395707769687266130899818243234204756499412 328
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 4 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 110358262319126835618581582317351908211161941048957108821429870135163224887570 315
UVM_ERROR @ 5498.630000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5498.630000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 28922895999905835034225212885631496626279143646586520907745939229400164226799 327
UVM_ERROR @ 10825.890000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10825.890000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 89162349344274493886717725955893765289443065875118357826239255917065736771800 325
UVM_ERROR @ 7439.615000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7439.615000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 62194525761870280562597774221171864466726635416162387424766508285965519215045 319
UVM_ERROR @ 7625.990000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7625.990000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 69098932237596385883701239711826171923636923890524439787146827133291196453386 369
UVM_INFO @ 7859.784500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 109152804587201725647105132645168562104338545568751117293484725540107681302308 369
UVM_INFO @ 10353.809097 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 65822235022017807575443168866581484774434882424780090479059736151016719567514 341
UVM_INFO @ 7028.649008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 60773438380549065458515468050161872048915020362068591659526592992404220109737 328
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 44591577701923462478377144335950882396766875922542779591399823251793642646806 328
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 15059134724709257744283749194321369943122838938885200575864784728486376412600 328
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 8599572680600583007991108662087852894278383920184519882565317557434957151670 316
UVM_ERROR @ 3268.775420 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3268.775420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 36916992902495136840977230776506434167127799661687733788456451090862757449224 312
UVM_ERROR @ 3150.017304 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3150.017304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 23970147890245205188641144145781928164479088128635046052802103464973632344034 313
UVM_ERROR @ 2593.064136 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2593.064136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 20639705866305733850857143387341689093068307607544418696530894397466081969497 380
UVM_ERROR @ 22637.794278 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 22637.794278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 59707894824743834746953621459598083437316723094360718498123873892176912131216 217
TL item was: req: (cip_tl_seq_item@34002) { a_addr: 'h107e8 a_data: 'he401034d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h18de3 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2635.684796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 43009112337516905328209188227671073694793768047208548890215720431745921579418 224
TL item was: req: (cip_tl_seq_item@31822) { a_addr: 'h105d4 a_data: 'h464f810d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h1a2e6 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2064.542405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 80862017684061767406238977691597457456599653224366741940661126682815426804262 364
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 68022084220401402203025475102350083315184801753230168420310656447069476761717 325
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 2837289332232434849048109798746354970265707809078290449216397123308141160029 368
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 8598850100057907829346524251181756385021839302514129960568412755391956659888 328
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 55340715582331738203391000570754449141787546029979007264339066085383536766304 301
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 27024603311445048951345661918016816487089185911510336967176659336725475828363 327
UVM_INFO @ 2670.922629 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 4401076216023959397637908328815698928639472380321894466556940672850139976226 309
UVM_INFO @ 2787.362850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 53852045316040406689116206233210451750151325844549457364378438248554569891457 342
UVM_INFO @ 6196.832808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 42459099272048777282278470994741443843799171920434847071481190166511581072512 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 23754222027997769153569656803833637422225714237011517777188199860761900192882 324
UVM_ERROR @ 6233.298325 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6233.298325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 79366237474106306968121263119080788869272305489418256386835207827003389678571 332
UVM_INFO @ 34831.430762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 109152124049448811770812254878462381584730287899143547430415707219167945126151 307
UVM_INFO @ 2749.969672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 68223544999948488077715448421099263886690326574893310666762242547434433115463 308
UVM_INFO @ 2911.126061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 52527418582121788881767776774111140229881455866456267573524149457371238819574 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 53626764926377084429067759662300239501027960398570094178658331362184741376260 343
UVM_INFO @ 3353.354684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 53284214759548859525827240922949883236784609842964968051555898550529849754932 278
UVM_INFO @ 13600.807170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 55427484204567930168762789244624321891262256358897465366455393219889659911164 312
UVM_INFO @ 2894.120000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 3841662777071255434561914395425701501585551680399888705671923003703572808921 319
UVM_INFO @ 3717.128000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 66781505599692935924606784406537237104342301910441849992349763115439353904277 327
UVM_INFO @ 9682.573439 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 66252326775456619822378959014337567179524354442729837535612898955040699010789 272
UVM_INFO @ 10010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 99335087590477837120434818199062992821402463619823762645282728308597628108161 325
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 38044296279666006815973522850677812867517423764598484955732760128565331039071 328
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) 1 test run
rom_e2e_jtag_debug_rma 115217126469439775588180610723838594104952442605592223318155298877954083890155 317
UVM_INFO @ 3427.421110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 112812332984306363467374348745065101625690193424065454262156334155020636504699 319
UVM_INFO @ 15255.776062 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 49497312032543763257306205809656344303997609247035725777171232086039924026992 327
UVM_ERROR @ 4405.184356 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4405.184356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---