Simulation Results: clkmgr

 
25/05/2026 15:30:28 DVSim: v1.49.1 sha: d315e4a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.05 %
  • code
  • 98.24 %
  • assert
  • 95.48 %
  • func
  • 85.42 %
  • line
  • 99.02 %
  • branch
  • 98.69 %
  • cond
  • 94.32 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.110s 27.165us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.850s 82.889us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.890s 14.734us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.550s 389.043us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.650s 116.926us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.640s 111.848us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.890s 14.734us 1 1 100.00
clkmgr_csr_aliasing 1.650s 116.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.780s 18.764us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.980s 60.865us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.840s 15.142us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.760s 16.529us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.110s 27.165us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 4.370s 803.602us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.690s 393.149us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 4.370s 803.602us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 26.880s 6280.373us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.730s 24.790us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.690s 188.328us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.690s 188.328us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.850s 82.889us 1 1 100.00
clkmgr_csr_rw 0.890s 14.734us 1 1 100.00
clkmgr_csr_aliasing 1.650s 116.926us 1 1 100.00
clkmgr_same_csr_outstanding 1.060s 53.435us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.850s 82.889us 1 1 100.00
clkmgr_csr_rw 0.890s 14.734us 1 1 100.00
clkmgr_csr_aliasing 1.650s 116.926us 1 1 100.00
clkmgr_same_csr_outstanding 1.060s 53.435us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 24.760s 10010.762us 0 1 0.00
clkmgr_tl_intg_err 1.350s 60.656us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 3.960s 1397.734us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 3.960s 1397.734us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 3.960s 1397.734us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 3.960s 1397.734us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 888.570s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.350s 60.656us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 4.370s 803.602us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.690s 393.149us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 3.960s 1397.734us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.990s 92.662us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.930s 55.403us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.770s 21.354us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.840s 65.965us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.820s 24.210us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.890s 14.734us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 24.760s 10010.762us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 14.734us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 14.734us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 24.760s 10010.762us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.590s 997.050us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 10.420s 1903.386us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 105357046938153447799536712205804971017260506459474157932274949195288283027649 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 72215138696089997386757642636729547457015828587326429173884530894817601311019 81
UVM_INFO @ 10010761500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---